JPS59118041U - calculator - Google Patents
calculatorInfo
- Publication number
- JPS59118041U JPS59118041U JP980683U JP980683U JPS59118041U JP S59118041 U JPS59118041 U JP S59118041U JP 980683 U JP980683 U JP 980683U JP 980683 U JP980683 U JP 980683U JP S59118041 U JPS59118041 U JP S59118041U
- Authority
- JP
- Japan
- Prior art keywords
- computer
- calculator
- priority interrupt
- watchdog timer
- restart
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Retry When Errors Occur (AREA)
- Debugging And Monitoring (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のシステムにおけるウォッチドッグタイマ
と計算機の関係を示した説明図、第２図はウォッチドッ
グタイマの動作を示Ｃたタイムチャート図、第３図は本
考案の一実施例のタイムチャート図、第４図は本考案の
一実施例を示すブロック図である。
１・・・計算機、２・・・ウォッチドッグタイマ、３・
・・リセット信号、４・・・タイムアツプ信号、５・・
・計算機再起動割込、６・・・クロック発生器、７・・
・１６ビツトプリセツトカウンタ、８・・・タイマ、９
・・・フリップフロップ、１０・・・ウォッチドッグタ
イマ設定時間。Figure 1 is an explanatory diagram showing the relationship between a watchdog timer and a computer in a conventional system, Figure 2 is a time chart diagram showing the operation of the watchdog timer, and Figure 3 is a time chart diagram of an embodiment of the present invention. The chart diagram and FIG. 4 are block diagrams showing one embodiment of the present invention. 1... Calculator, 2... Watchdog timer, 3.
...Reset signal, 4...Time-up signal, 5...
・Computer restart interrupt, 6...Clock generator, 7...
・16-bit preset counter, 8...timer, 9
...Flip-flop, 10...Watchdog timer setting time.
Claims (1)
し、かつ該計算機の動作を監視するためのウォッチドッ
グタイマを有する計算機において、該ウオッチドックタ
イマのタイムアツプ時、又は、その一定時間前に計算機
に優先割込を発生させることにより、計算機の再起動を
可能としたことを特徴とすを計算機。In a stored program type computer that has a priority interrupt function and a watchdog timer for monitoring the operation of the computer, the computer A computer characterized by making it possible to restart the computer by generating a priority interrupt.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP980683U JPS59118041U (en) | 1983-01-28 | 1983-01-28 | calculator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP980683U JPS59118041U (en) | 1983-01-28 | 1983-01-28 | calculator |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59118041U true JPS59118041U (en) | 1984-08-09 |
Family
ID=30141253
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP980683U Pending JPS59118041U (en) | 1983-01-28 | 1983-01-28 | calculator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59118041U (en) |
-
1983
- 1983-01-28 JP JP980683U patent/JPS59118041U/en active Pending
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