JPS6095638U - Control device - Google Patents

Control device

Info

Publication number
JPS6095638U
JPS6095638U JP18758083U JP18758083U JPS6095638U JP S6095638 U JPS6095638 U JP S6095638U JP 18758083 U JP18758083 U JP 18758083U JP 18758083 U JP18758083 U JP 18758083U JP S6095638 U JPS6095638 U JP S6095638U
Authority
JP
Japan
Prior art keywords
cpu
clock
frequency
control device
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18758083U
Other languages
Japanese (ja)
Inventor
吉岡 道雄
大村 久英
Original Assignee
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 横河電機株式会社 filed Critical 横河電機株式会社
Priority to JP18758083U priority Critical patent/JPS6095638U/en
Publication of JPS6095638U publication Critical patent/JPS6095638U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案にかかる制御装置の構成を示した概念図
、第2図は本考案にかかる制御装置の一実施例の具体的
な構成を示したブロック図、第3、図は第2図の制御装
置の動作を示したフローチャートである。 10・・・CPU、20・・・可変周波数クロック回路
、30・・・CPU監視回路。
FIG. 1 is a conceptual diagram showing the configuration of a control device according to the present invention, FIG. 2 is a block diagram showing a specific configuration of an embodiment of the control device according to the present invention, and FIG. 3 is a flowchart showing the operation of the control device shown in the figure. 10...CPU, 20...Variable frequency clock circuit, 30...CPU monitoring circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] CPUクロックが与えられることによって動作するCP
Uと、該CPUにCPUクロックを出力するととにこの
CPUクロックの周波数が種々の値に゛ 選択可能であ
る可変周波数クロック回路と、前記CPUの動作を監視
しこの動作の良否に応じて前記可変周波数クロック回路
に周波数選択信号を送りCPUを動作させるのに最適な
CPUクロックの周波数を選択させるCPU監視回路と
を具備したことを特徴とする制御装置。
A CPU that operates by being given a CPU clock
a variable frequency clock circuit that outputs a CPU clock to the CPU so that the frequency of the CPU clock can be selected from various values; A control device comprising: a CPU monitoring circuit that sends a frequency selection signal to a frequency clock circuit to select an optimal CPU clock frequency for operating a CPU.
JP18758083U 1983-12-05 1983-12-05 Control device Pending JPS6095638U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18758083U JPS6095638U (en) 1983-12-05 1983-12-05 Control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18758083U JPS6095638U (en) 1983-12-05 1983-12-05 Control device

Publications (1)

Publication Number Publication Date
JPS6095638U true JPS6095638U (en) 1985-06-29

Family

ID=30404875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18758083U Pending JPS6095638U (en) 1983-12-05 1983-12-05 Control device

Country Status (1)

Country Link
JP (1) JPS6095638U (en)

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