JPS58101233U - Standby mode control device - Google Patents

Standby mode control device

Info

Publication number
JPS58101233U
JPS58101233U JP19769481U JP19769481U JPS58101233U JP S58101233 U JPS58101233 U JP S58101233U JP 19769481 U JP19769481 U JP 19769481U JP 19769481 U JP19769481 U JP 19769481U JP S58101233 U JPS58101233 U JP S58101233U
Authority
JP
Japan
Prior art keywords
oscillator
control device
standby
mode control
standby mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP19769481U
Other languages
Japanese (ja)
Other versions
JPH035948Y2 (en
Inventor
中森　勉
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP19769481U priority Critical patent/JPS58101233U/en
Publication of JPS58101233U publication Critical patent/JPS58101233U/en
Application granted granted Critical
Publication of JPH035948Y2 publication Critical patent/JPH035948Y2/ja
Granted legal-status Critical Current

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  • Power Sources (AREA)
  • Microcomputers (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案の一実施例を示す概略ブロック図、第２
図はスタンバイモードのフローチャート、第３図はスタ
ンバイ制御ロジックの説明図、第４図はディレィタイマ
の説明図である。 −図中、２はスタンバイ制御ロジック、３は発振器、４
はクロック分周／制御回路、５はスタンバイ解除端子、
６はディレィタイマである。Fig. 1 is a schematic block diagram showing one embodiment of the present invention;
FIG. 3 is a flowchart of the standby mode, FIG. 3 is an explanatory diagram of the standby control logic, and FIG. 4 is an explanatory diagram of the delay timer. - In the figure, 2 is standby control logic, 3 is oscillator, 4 is
is a clock division/control circuit, 5 is a standby release terminal,
6 is a delay timer.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] スタンバイ期間には発振器の動作を停止させ、且つ外部
からのスタンバイ解除信号を受けて該発振器の動作を再
開させる１チツプマイクロコンピユータのスタンバイモ
ード制御装置において、該発振器の始動と同期して動作
を開始するディレィタイマを通常のプログラム実行に使
用されるカウンタ類とは独立した機能として設け、そし
て該ディレィタイマによって該発振器の動作が再開され
てから一定時間はスタンバイ制御に不要な部分へのクロ
ック供給を禁止するようにしてなることを特徴とするス
タンバイモード制御装置。In a standby mode control device for a one-chip microcomputer that stops the operation of an oscillator during a standby period and resumes operation of the oscillator upon receiving an external standby release signal, the operation starts in synchronization with the start of the oscillator. A delay timer is provided as a function independent of the counters used for normal program execution, and the delay timer prevents clock supply to parts unnecessary for standby control for a certain period of time after the oscillator resumes operation. A standby mode control device characterized in that:
JP19769481U 1981-12-25 1981-12-25 Standby mode control device Granted JPS58101233U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19769481U JPS58101233U (en) 1981-12-25 1981-12-25 Standby mode control device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19769481U JPS58101233U (en) 1981-12-25 1981-12-25 Standby mode control device

Publications (2)

Publication Number Publication Date
JPS58101233U true JPS58101233U (en) 1983-07-09
JPH035948Y2 JPH035948Y2 (en) 1991-02-15

Family

ID=30110907

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19769481U Granted JPS58101233U (en) 1981-12-25 1981-12-25 Standby mode control device

Country Status (1)

Country Link
JP (1) JPS58101233U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6986070B2 (en) 2000-12-28 2006-01-10 Denso Corporation Microcomputer that cooperates with an external apparatus to be driven by a drive signal

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5642827A (en) * 1979-09-18 1981-04-21 Nec Corp Data processor
JPS56147216A (en) * 1980-04-17 1981-11-16 Nec Corp Microcomputer system
JPS56147220A (en) * 1980-04-17 1981-11-16 Nec Corp Clock controller

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5642827A (en) * 1979-09-18 1981-04-21 Nec Corp Data processor
JPS56147216A (en) * 1980-04-17 1981-11-16 Nec Corp Microcomputer system
JPS56147220A (en) * 1980-04-17 1981-11-16 Nec Corp Clock controller

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6986070B2 (en) 2000-12-28 2006-01-10 Denso Corporation Microcomputer that cooperates with an external apparatus to be driven by a drive signal

Also Published As

Publication number Publication date
JPH035948Y2 (en) 1991-02-15

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