JPS58178697U - timer device - Google Patents
timer deviceInfo
- Publication number
- JPS58178697U JPS58178697U JP7604082U JP7604082U JPS58178697U JP S58178697 U JPS58178697 U JP S58178697U JP 7604082 U JP7604082 U JP 7604082U JP 7604082 U JP7604082 U JP 7604082U JP S58178697 U JPS58178697 U JP S58178697U
- Authority
- JP
- Japan
- Prior art keywords
- memory counter
- output
- flash pulse
- timer
- turned
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electric Clocks (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来装置の一例を概略的に示す回路構成図、第
2図はこの考案の一実施例を示す回路構成図である。
10はタイマ、11は表示器、12はメモリカウンタ、
13,15はノア回路、17はアンド回路、19は手動
スイッチである。FIG. 1 is a circuit diagram schematically showing an example of a conventional device, and FIG. 2 is a circuit diagram showing an embodiment of this invention. 10 is a timer, 11 is a display, 12 is a memory counter,
13 and 15 are NOR circuits, 17 is an AND circuit, and 19 is a manual switch.
Claims (1)
を発生する機能を有するタイ与と、複数日を予約設定で
き且つ上記タイマの表示用駆動信号力用変り用クロック
信号として供給されると共に停電又は電源投入時上記フ
ラッシュパルスが供給されるメモリカウンタと、該メモ
リカウンタの出力に応答して上記タイマの出力を導出す
るゲート回路と、上記メモリカウンタの出力を検出して
該メモリカウンタへ供給されるクロック信号又はフラッ
シュパルスを抑制するトラップゲート手段°とを具備し
て成るタイマ装置。The timer has the function of generating a flash pulse for display blinking during a power outage or when the power is turned on, and can be reserved for multiple days. a memory counter to which the flash pulse is supplied when turned on; a gate circuit that derives the output of the timer in response to the output of the memory counter; and a clock that detects the output of the memory counter and supplies it to the memory counter. and trap gate means for suppressing the signal or flash pulse.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7604082U JPS58178697U (en) | 1982-05-24 | 1982-05-24 | timer device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP7604082U JPS58178697U (en) | 1982-05-24 | 1982-05-24 | timer device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS58178697U true JPS58178697U (en) | 1983-11-29 |
JPS6217755Y2 JPS6217755Y2 (en) | 1987-05-07 |
Family
ID=30085365
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP7604082U Granted JPS58178697U (en) | 1982-05-24 | 1982-05-24 | timer device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58178697U (en) |
-
1982
- 1982-05-24 JP JP7604082U patent/JPS58178697U/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6217755Y2 (en) | 1987-05-07 |
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