JPH01135553U - - Google Patents
Info
- Publication number
- JPH01135553U JPH01135553U JP2985588U JP2985588U JPH01135553U JP H01135553 U JPH01135553 U JP H01135553U JP 2985588 U JP2985588 U JP 2985588U JP 2985588 U JP2985588 U JP 2985588U JP H01135553 U JPH01135553 U JP H01135553U
- Authority
- JP
- Japan
- Prior art keywords
- control program
- interrupt
- mode
- storage unit
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 2
- 230000010355 oscillation Effects 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図はこの考案の一実施例の回路構成を示す
ブロツク図、第２図は同実施例に用いられるテス
ト処理制御部を示す図、第３図は同実施例を説明
するためのタイムチヤート、第４図は同実施例を
説明するためのフローチヤートである。
１…ＣＰＵ、４…ＲＯＭ、５…オペレーシヨン
デコーダ、６…ＡＬＵ、７…テスト処理制御部、
８…アドレスレジスタ、９…汎用レジスタ、１０
…アドレス制御部、１１…発振部、１２，２０，
２３，２４…フリツプフロツプ、１３，１４，１
５，１７，１８…アンドゲート、１６…オアゲー
ト、２２…インバータ、２６…分周回路、２７…
ジヤンプ先アドレス記憶部。
Fig. 1 is a block diagram showing the circuit configuration of an embodiment of this invention, Fig. 2 is a diagram showing a test processing control section used in the embodiment, and Fig. 3 is a time chart for explaining the embodiment. , FIG. 4 is a flowchart for explaining the same embodiment. 1... CPU, 4... ROM, 5... operation decoder, 6... ALU, 7... test processing control unit,
8...Address register, 9...General-purpose register, 10
... Address control section, 11... Oscillation section, 12, 20,
23, 24...Flip-flop, 13, 14, 1
5, 17, 18... AND gate, 16... OR gate, 22... Inverter, 26... Frequency dividing circuit, 27...
Jump destination address storage.
Claims (1)
各種レジスタおよび演算部を有する中央演算装置
と、上記記憶部の制御プログラムをテストするた
めのテストモードを指定するモード指定手段と、
このモード指定手段によりテストモードが指定さ
れた状態で上記中央演算装置による制御プログラ
ムの１ステツプ処理毎に割込み処理を実行する割
込み実行手段と、この割込み実行手段による割込
み処理により得られた上記制御プログラムの実行
データを出力する出力手段とを具備したことを特
徴とするデバツク回路。 a storage unit that stores at least a control program;
a central processing unit having various registers and an arithmetic unit; a mode specifying means for specifying a test mode for testing a control program in the storage unit;
an interrupt execution means for executing interrupt processing for each step of the control program by the central processing unit in a state where the test mode is specified by the mode specification means; and the control program obtained by the interrupt processing by the interrupt execution means. 1. A debugging circuit comprising: output means for outputting execution data of the debugging circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2985588U JPH01135553U (en) | 1988-03-08 | 1988-03-08 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2985588U JPH01135553U (en) | 1988-03-08 | 1988-03-08 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01135553U true JPH01135553U (en) | 1989-09-18 |
Family
ID=31254431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2985588U Pending JPH01135553U (en) | 1988-03-08 | 1988-03-08 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01135553U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49120559A (en) * | 1973-03-16 | 1974-11-18 |
-
1988
- 1988-03-08 JP JP2985588U patent/JPH01135553U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49120559A (en) * | 1973-03-16 | 1974-11-18 |
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