JPH03113438U - - Google Patents
Info
- Publication number
- JPH03113438U JPH03113438U JP2113790U JP2113790U JPH03113438U JP H03113438 U JPH03113438 U JP H03113438U JP 2113790 U JP2113790 U JP 2113790U JP 2113790 U JP2113790 U JP 2113790U JP H03113438 U JPH03113438 U JP H03113438U
- Authority
- JP
- Japan
- Prior art keywords
- register
- address
- dump
- contents
- rom
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Description
図はこの考案のＲＯＭプログラムデバツグ装置
の一実施例を示す図であり、１は表示装置、２は
レジスタダンプアドレス設定装置、３はプログラ
ムカウンタ、４はレジスタダンプアドレス保持レ
ジスタ、５は比較器、６はレジスタダンプ指示装
置、７は演算装置、８はレジスタ、Ａはレジスタ
ダンプ指示信号である。
The figure shows an embodiment of the ROM program debugging device of this invention, in which 1 is a display device, 2 is a register dump address setting device, 3 is a program counter, 4 is a register dump address holding register, and 5 is a comparator. , 6 is a register dump instruction device, 7 is an arithmetic unit, 8 is a register, and A is a register dump instruction signal.
Claims (1)
ラムをデバツクするために、特定のアドレスを実
行したとき、レジスタの内容を表示させるため、
そのアドレスを設定するレジスタダンプアドレス
設定装置と、このレジスタダンプアドレス設定装
置から設定したレジスタダンプアドレスを保持す
るレジスタダンプアドレス保持レジスタと、プロ
グラムの実行アドレスを保持しているプログラム
カウンタと、このプログラムカウンタの内容と上
記レジスタダンプアドレス保持レジスタの内容の
比較を行う比較器と、この比較器からの比較信号
を入力し、レジスタダンプ指示信号を発生させる
レジスタダンプ指示装置と、演算を行う演算装置
と、この演算装置からの出力を保持するレジスタ
と、レジスタダンプ指示信号発生時、レジスタの
内容を表示する表示装置を有するＲＯＭプログラ
ムデバツグ装置において、ＲＯＭ上のプログラム
の実行中にレジスタの内容を表示することが可能
であることを特徴としたＲＯＭプログラムデバツ
グ装置。 To debug programs on ROM (read-only memory), display the contents of registers when a specific address is executed.
A register dump address setting device that sets the address, a register dump address holding register that holds the register dump address set by this register dump address setting device, a program counter that holds the program execution address, and this program counter. a comparator that compares the contents of the register dump address holding register with the contents of the register dump address holding register, a register dump instruction device that inputs the comparison signal from the comparator and generates a register dump instruction signal, and an arithmetic device that performs an operation. In a ROM program debugging device that has a register that holds the output from this arithmetic unit and a display device that displays the contents of the register when a register dump instruction signal is generated, the contents of the register are displayed while the program on the ROM is being executed. A ROM program debugging device characterized by being capable of
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2113790U JPH03113438U (en) | 1990-03-02 | 1990-03-02 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2113790U JPH03113438U (en) | 1990-03-02 | 1990-03-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03113438U true JPH03113438U (en) | 1991-11-20 |
Family
ID=31524195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2113790U Pending JPH03113438U (en) | 1990-03-02 | 1990-03-02 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03113438U (en) |
-
1990
- 1990-03-02 JP JP2113790U patent/JPH03113438U/ja active Pending
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