JPH04148244A - Software evaluating device - Google Patents

Abstract

PURPOSE:To monitor the state of the inside of an emulation chip in real time by providing an internal bus interface to output emulation chip internal data to the outside at the time of the execution of an evaluating program by the emulation chip. CONSTITUTION:The execution of the evaluating program is realized by synchronizing the emulation chip 7, a monitor ROM 8 and a ROM 9 with one another by a reset signal for a peripheral circuit 11, and executing the evaluating program from the head address of the evaluating program in the ROM 9 by the emulation chip 7. At that time, a write signal to a RAM and a register in the emulation chip 7 and the values of a data bus, an address bus, and a program counter, etc., are outputted through the internal bus interface 10. Thus, even during the execution of the evaluating program by the emulation chip 7, the internal data of the emulation chip 7 can be monitored.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a software evaluation device, and more particularly to a software evaluation device used for monitoring an internal bus of a single-chip microcomputer in real time.

[Conventional technology]

As shown in FIG. 3, a conventional single-chip macrocomputer software evaluation device includes an evaluation chip 21 that emulates the single-chip macrocomputer, and a monitor ROM that controls the evaluation chip 12.
13, and a RAM 14 for storing an evaluation program.
It is configured to include an interface circuit 15 corresponding to a host machine and a peripheral circuit 16.

In the software evaluation apparatus having such a configuration, an evaluation program is stored in the RAM 14 from the host machine via the interface circuit 15. Furthermore, the evaluation program is executed by sending commands from the host machine to the monitor ROM 1 via the interface circuit 15.
3, and under the control of the monitor ROM 13, the RA
10 grams for evaluation stored in M14 is transferred to Evachip 1
This is realized by executing 2. Furthermore, when transferring the internal data of the Evachip 12 to the host machine, execution of the evaluation program stored in the RAM 14 is temporarily stopped, and the data in the Evachip 12 is transferred to the host machine via the interface circuit 15. do.

[Problem to be solved by the invention]

In the above-mentioned conventional software evaluation device, when attempting to transfer data in the Eva chip, for example, RAM or register values in the Eva chip, to the host machine, the execution of the evaluation program is stopped first, and the data in the Eva chip is transferred to the host machine. The system has become a system that must concentrate on transferring data.

Therefore, if you try to view the data in the Eva-chip at any time while running the evaluation program, the Eva-chip will intermittently repeat the execution of the evaluation program and the data transfer. , there is a drawback that there is a large difference in operational timing, etc. between emulation using an Eva chip.

[Means to solve the problem]

The software evaluation device of the present invention includes, in one chip,
In a software evaluation device having an evaluation chip that emulates a single-chip microcomputer that has at least a built-in ROM or RAM, the RAM or ROM stores a predetermined evaluation program, and the execution operation of the evaluation program by the evaluation chip is controlled. and an internal bus interface that outputs internal data of the Eva-chip to the outside when the Eva-chip executes the evaluation program.

〔Example〕

Next, the present invention will be explained with reference to the drawings. FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, this embodiment includes an Eva chip 1,
Monitor ROM2, RAM3, and interface circuit 4
, an internal bus interface 5 , and a peripheral circuit 6 .

The evaluation program is stored in the RAM 3 from the host machine via the interface circuit 4, as in the conventional example. When executing this evaluation program, an execution command from the host machine is input to the monitor ROM 2 via the interface circuit 4. Then, under the control of the monitor ROM 2, the RA
The evaluation program stored in M3 is executed.

At that time, from the Eva chip 1, the RAM in the Eva chip 1 is
Alternatively, write signals to registers, data buses, address buses, program counter values, etc. are output.

In addition, the monitor RO can be controlled by commands from the host machine.
M2: When an enable signal is output to the internal bus interface 5, write signals to the RAM or registers in the EV chip 1, as well as data buses, address buses, program values, etc. are sent via the internal bus interface 5. is output to the outside.

As mentioned above, the emulation operation of the Eva-chip 1 can be stopped by measuring the internal data of the Eva-chip 1 output via the internal bus interface 5 using a logic analyzer or the like triggered by the write signal. can be monitored on a real-time basis. Also, when executing a program at a specific address in RAMB for monitor ROM 2, or when accessing RAM or registers at a specific address in Evachip 1, the enable signal is sent from monitor ROM 2 to internal bus interface 5. By setting the signal so that it is output, the data in the EV chip 1 can be monitored only when necessary.

Next, a second embodiment of the present invention will be described with reference to FIG. As shown in FIG. 2, this embodiment includes an evaluation chip 7, a monitor ROM 8, a ROM 9, an internal bus interface 1O, and a peripheral circuit 11.

In FIG. 2, the evaluation program is executed by synchronizing the evaluation program 7, monitor ROM 8, and ROM 9 with a reset signal from the peripheral circuit 11, and executing the evaluation program from the first address in ROMQ by the evaluation chip 7. This is realized by At this time, write signals, data buses, address buses, program counter values, etc. to the RAM and registers in the evaluation chip 7 are outputted via the internal bus interface 10. Therefore, even while the evaluation program is being executed by the Eva-chip 7, it is possible to monitor the internal data of the Eva-chip 7. Note that in this case, no command from the host machine is required. As described above, in the case of the second embodiment, the evaluation program can be executed and the inside of the evaluation chip 7 can be monitored on a real-time basis without using a host machine.

〔Effect of the invention〕

As described above in detail, the present invention is capable of checking the internal state of an evaluation chip included in a software evaluation device for a single-chip microcomputer on a real-time basis, thereby dynamically controlling the operation of an evaluation program. This has the effect of significantly improving the work efficiency of daybugs and the like.

[Brief explanation of drawings]

FIGS. 1 and 2 are block diagrams showing first and second embodiments of the present invention, respectively. FIG. 3 is a block diagram of a conventional example. In the figure, 1, 7.12 --- Eva chip, 2
゜8.13...Monitor ROM, 3,14...
...RAM, 4゜15...Interface circuit, 5,10...Internal interface, 6.1
1.16...Peripheral circuit, 9...ROM
.

Claims (1)

[Scope of Claims] In a software evaluation device having an evaluation chip that emulates a single-chip microcomputer that has at least a ROM or RAM built-in in one chip, the RAM or ROM stores a predetermined evaluation program.
a monitor ROM that controls the execution operation of the evaluation program by the evaluation chip; an internal bus interface that outputs internal data of the evaluation chip from the evaluation chip to the outside when the evaluation program is executed by the evaluation chip; A software evaluation device comprising: