JPS639651U - - Google Patents
Info
- Publication number
- JPS639651U JPS639651U JP10155986U JP10155986U JPS639651U JP S639651 U JPS639651 U JP S639651U JP 10155986 U JP10155986 U JP 10155986U JP 10155986 U JP10155986 U JP 10155986U JP S639651 U JPS639651 U JP S639651U
- Authority
- JP
- Japan
- Prior art keywords
- ram
- rom
- test mode
- decoded
- address
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図は本考案の一実施例のブロツク図、第２
図は従来のテスト機能を有するマイクロコンピユ
ータの主要部の一例のブロツク図である。
１……汎用入出力端子、２……テスト端子、３
……プログラム・カウンタ、４……ＲＡＭ、５…
…命令デコーダ、６……ＲＯＭ、７……データ・
ポインタ、８……制御回路、９……インクリメン
タ、１１……制御信号、１２，１３……テスト制
御信号、２１……データバス、２２……アドレス
バス。
Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a block diagram of an example of the main parts of a conventional microcomputer having a test function. 1...General-purpose input/output terminal, 2...Test terminal, 3
...Program counter, 4...RAM, 5...
...Instruction decoder, 6...ROM, 7...Data
Pointer, 8... Control circuit, 9... Incrementer, 11... Control signal, 12, 13... Test control signal, 21... Data bus, 22... Address bus.
Claims (1)
るテスト端子と、テストモード時に外部より命令
を取込む汎用入出力端子と、前記ＲＡＭのアドレ
スを指定するデータ・ポインタと、該データ・ポ
インタの内容を順次増加するインクリメンタと、
前記ＲＯＭのアドレスを指定するプログラム・カ
ウンタと、通常動作時は前記プログラム・カウン
タにより指定される前記ＲＯＭの出力データを命
令コードとして解読したテスト・モード時は前記
ＲＡＭの出力データを命令コードとして解読する
命令デコーダとを含むことを特徴とするマイクロ
コンピユータ。 ROM, RAM, a test terminal for setting the test mode, a general-purpose input/output terminal for receiving instructions from the outside in the test mode, a data pointer for specifying the address of the RAM, and the contents of the data pointer. an incrementer that increases sequentially,
A program counter that specifies the address of the ROM, and during normal operation, the output data of the ROM specified by the program counter is decoded as an instruction code.In a test mode, the output data of the RAM is decoded as an instruction code. A microcomputer comprising: an instruction decoder that performs the following operations.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10155986U JPS639651U (en) | 1986-07-01 | 1986-07-01 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10155986U JPS639651U (en) | 1986-07-01 | 1986-07-01 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS639651U true JPS639651U (en) | 1988-01-22 |
Family
ID=30972399
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10155986U Pending JPS639651U (en) | 1986-07-01 | 1986-07-01 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS639651U (en) |
-
1986
- 1986-07-01 JP JP10155986U patent/JPS639651U/ja active Pending
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