JPS58124837U - Integrated circuit with built-in memory - Google Patents
Integrated circuit with built-in memoryInfo
- Publication number
- JPS58124837U JPS58124837U JP2253182U JP2253182U JPS58124837U JP S58124837 U JPS58124837 U JP S58124837U JP 2253182 U JP2253182 U JP 2253182U JP 2253182 U JP2253182 U JP 2253182U JP S58124837 U JPS58124837 U JP S58124837U
- Authority
- JP
- Japan
- Prior art keywords
- built
- memory
- integrated circuit
- predetermined data
- logical operation
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Storage Device Security (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来の１チツプマイクロコンピユータのブロッ
ク図、第２図は本考案の一実施例の要部回路１１７２図
、第３図は第２図中の演算回路部 、の−具体例を
示すブロック図である。
１．１′・・・・・・プログラムカウンタ、２． ２’
・・・・・・ＲＯＭ、３．３’・・・・・・アドレス線
、４． ４’・・・・・・ＲＯＭデータ出力線、５．
５’・・・・・′・ファンクシ ′ヨンブロック、６．
６’・・・・・・出力回路、７，７′・・・・・・出力
端子、８・・・・・・演算回路、９・・・・・・製造工
程におけるマスク焼付けによる一定値設定回路、１０・
・・設定値出力線、１１・・・・・・出力埜止線。Fig. 1 is a block diagram of a conventional one-chip microcomputer, Fig. 2 is a diagram of a main circuit 1172 of an embodiment of the present invention, and Fig. 3 is a concrete example of the arithmetic circuit section in Fig. 2. It is a block diagram. 1.1'...Program counter, 2. 2'
...ROM, 3.3'...Address line, 4. 4'...ROM data output line, 5.
5'...'・Funkushi 'Yon block, 6.
6'...Output circuit, 7,7'...Output terminal, 8...Arithmetic circuit, 9...Constant value setting by mask baking in manufacturing process circuit, 10・
...Set value output line, 11...Output stop line.
Claims (1)
手段と、読み出されたメモリ内容と前記所定のデニタと
を論理演算する手段と、この論理演算結果を外部へ出力
する手段とを有することを特徴とするメモリ内蔵集積回
路。The method includes means for reading memory contents, means for holding predetermined data, means for performing a logical operation on the read memory contents and the predetermined data, and means for outputting the result of the logical operation to the outside. Integrated circuit with built-in memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2253182U JPS58124837U (en) | 1982-02-19 | 1982-02-19 | Integrated circuit with built-in memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2253182U JPS58124837U (en) | 1982-02-19 | 1982-02-19 | Integrated circuit with built-in memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58124837U true JPS58124837U (en) | 1983-08-25 |
Family
ID=30034608
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2253182U Pending JPS58124837U (en) | 1982-02-19 | 1982-02-19 | Integrated circuit with built-in memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58124837U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313200A (en) * | 1986-07-03 | 1988-01-20 | Nec Corp | Integrated circuit |
-
1982
- 1982-02-19 JP JP2253182U patent/JPS58124837U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6313200A (en) * | 1986-07-03 | 1988-01-20 | Nec Corp | Integrated circuit |
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