JPS5836402U - Sequencer - Google Patents
SequencerInfo
- Publication number
- JPS5836402U JPS5836402U JP13097981U JP13097981U JPS5836402U JP S5836402 U JPS5836402 U JP S5836402U JP 13097981 U JP13097981 U JP 13097981U JP 13097981 U JP13097981 U JP 13097981U JP S5836402 U JPS5836402 U JP S5836402U
- Authority
- JP
- Japan
- Prior art keywords
- sequencer
- utility
- model registration
- mode
- program
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Safety Devices In Control Systems (AREA)
- Programmable Controllers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来のシーケンサの内部回路図、第2図は従来
のシーケンサでのメモリマツプの内容ヲ示す図、第3図
は本考案になるシーケンサの内部回路図、第4図は本考
案になるシーケンサでのメモリマツプの内容を示す図、
第5図は本考案になるシーケンサの変形例を示す回路図
である。
1・・・・・・処理装置、2・・・・・・メモリ、3・
・・・・・プロセスデータ入出力部、4・・・・・・ア
ドレスバス、5・・・・・・データバス、6・・・・・
・アドレスバス、7・・・・・・選択信号、8・・・・
・・エンコーダ回路、9・・・・・・加算回路、10・
・・・・・モディファイアドレス出力、11・・・・・
・バイアスアドレス出力、12・・・・・・プロセス入
出力信号、13・・・・・・入出カポ−ドアドレスバス
。Figure 1 is an internal circuit diagram of a conventional sequencer, Figure 2 is a diagram showing the contents of a memory map in a conventional sequencer, Figure 3 is an internal circuit diagram of a sequencer according to the present invention, and Figure 4 is a diagram according to the present invention. Diagram showing the contents of the memory map in the sequencer,
FIG. 5 is a circuit diagram showing a modification of the sequencer according to the present invention. 1...Processing device, 2...Memory, 3.
...Process data input/output section, 4...Address bus, 5...Data bus, 6...
・Address bus, 7...Selection signal, 8...
... Encoder circuit, 9... Addition circuit, 10.
...Modify address output, 11...
- Bias address output, 12...process input/output signal, 13...input/output coupler address bus.
Claims (1)
いてプラントの一部を1台のシーケンサで制御する場合
に、プラントのプロセスモードの移行と同時にシーケン
サの実行モードを変更可能ならしめるように、モード移
行を示すプロセス信号を取込み、この信号によりシーケ
ンサ内のプロセス制御プログラムを選択変更する事を特
徴とするシーケンサ。 2 上記1の実用新案登録請求の範囲第1項において、
シーケンサのもつ複数のプロセス制御プログラムのうち
1つのプログラムのみを実行モードにする事を特徴とす
るシーケンサ。 3 実用新案登録請求の範囲第1項または第2項におい
て、外部プロセス入力信号をデコーダ等のハード構成で
プログラムのアドレスを指定する事に使用する事を特徴
とするシーケンサ。[Claims for Utility Model Registration] 1. When a part of a plant consisting of multiple process modes is controlled by one sequencer, if it is possible to change the execution mode of the sequencer at the same time as the process mode of the plant is shifted. A sequencer characterized in that it takes in a process signal indicating a mode transition and selectively changes a process control program within the sequencer using this signal. 2 In paragraph 1 of claims for utility model registration in 1 above,
A sequencer characterized in that only one program out of a plurality of process control programs possessed by the sequencer is put into execution mode. 3. A sequencer according to claim 1 or 2 of the utility model registration claim, characterized in that an external process input signal is used to designate a program address with a hardware configuration such as a decoder.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13097981U JPS5836402U (en) | 1981-09-04 | 1981-09-04 | Sequencer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13097981U JPS5836402U (en) | 1981-09-04 | 1981-09-04 | Sequencer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5836402U true JPS5836402U (en) | 1983-03-09 |
Family
ID=29924581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP13097981U Pending JPS5836402U (en) | 1981-09-04 | 1981-09-04 | Sequencer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5836402U (en) |
-
1981
- 1981-09-04 JP JP13097981U patent/JPS5836402U/en active Pending
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