JPH038782U - - Google Patents
Info
- Publication number
- JPH038782U JPH038782U JP6958089U JP6958089U JPH038782U JP H038782 U JPH038782 U JP H038782U JP 6958089 U JP6958089 U JP 6958089U JP 6958089 U JP6958089 U JP 6958089U JP H038782 U JPH038782 U JP H038782U
- Authority
- JP
- Japan
- Prior art keywords
- parity
- circuit
- controlled
- circuit section
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
- Test And Diagnosis Of Digital Computers (AREA)
Description
第１図はこの考案の一実施例の構成を示すブロ
ツク図、第２図はＬＳＩの機能試験の概念を説明
するためのブロツクである。
１１……演算回路、１２……データ・バス制御
回路、１３……ＣＰＵレジスタ群、１４……アド
レス制御回路、１５……命令レジスタ、（１１〜
１５が被制御回路部）、１６……命令デコーダ・
ＣＰＵ制御回路、（制御回路部）、２０……パリ
テイ検出回路、Ｔｔ……試験用出力端子。
FIG. 1 is a block diagram showing the configuration of an embodiment of this invention, and FIG. 2 is a block diagram for explaining the concept of LSI functional testing. 11...Arithmetic circuit, 12...Data bus control circuit, 13...CPU register group, 14...Address control circuit, 15...Instruction register, (11--
15 is a controlled circuit section), 16 is an instruction decoder/
CPU control circuit, (control circuit section), 20... Parity detection circuit, Tt... Test output terminal.
Claims (1)
から出力される内部制御信号によつて制御される
被制御回路部とを有する半導体集積回路において
、 前記内部制御信号のパリテイを検出するパリテ
イ検出回路と、 前記パリテイ検出回路から出力されるパリテイ
信号を外部へ出力する試験用出力端子と、 を具備することを特徴とする半導体集積回路。[Claims for Utility Model Registration] A semiconductor integrated circuit having at least a control circuit section and a controlled circuit section controlled by an internal control signal output from the control circuit section, A semiconductor integrated circuit comprising: a parity detection circuit that detects parity; and a test output terminal that outputs a parity signal output from the parity detection circuit to the outside.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6958089U JPH038782U (en) | 1989-06-14 | 1989-06-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6958089U JPH038782U (en) | 1989-06-14 | 1989-06-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH038782U true JPH038782U (en) | 1991-01-28 |
Family
ID=31605009
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6958089U Pending JPH038782U (en) | 1989-06-14 | 1989-06-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH038782U (en) |
-
1989
- 1989-06-14 JP JP6958089U patent/JPH038782U/ja active Pending
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