JPH01127045U - - Google Patents
Info
- Publication number
- JPH01127045U JPH01127045U JP2413988U JP2413988U JPH01127045U JP H01127045 U JPH01127045 U JP H01127045U JP 2413988 U JP2413988 U JP 2413988U JP 2413988 U JP2413988 U JP 2413988U JP H01127045 U JPH01127045 U JP H01127045U
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- central processing
- reset
- address
- peripheral device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Bus Control (AREA)
Description
第１図は本考案の一実施例のコンピユータシス
テムの構成を示すブロツク図、第２図は本実施例
のアドレス記憶回路の構成例を示す論理回路図、
第３図は本実施例の動作を説明するためのアドレ
ス記憶タイミングチヤート、第４図は従来構成を
示すブロツク図である。
１０…ＣＰＵ（中央処理装置）、１１―１〜１
１―ｍ…周辺デバイス、１１ａ…アドレス記憶回
路（制御回路）、１２…アドレス記憶レジスタ（
制御回路）、…システムリセツト端、
…リセツト入力端、…リセツト出力
端。
FIG. 1 is a block diagram showing the configuration of a computer system according to an embodiment of the present invention, and FIG. 2 is a logic circuit diagram showing an example of the configuration of an address storage circuit according to the present invention.
FIG. 3 is an address storage timing chart for explaining the operation of this embodiment, and FIG. 4 is a block diagram showing a conventional configuration. 10...CPU (central processing unit), 11-1 to 1
1-m...Peripheral device, 11a...Address storage circuit (control circuit), 12...Address storage register (
control circuit), ...system reset end,
...Reset input terminal, ...Reset output terminal.
Claims (1)
と、各々リセツト入力端とリセツト出力端とを有
し前記中央処理装置にアドレスバスを介して接続
された複数の周辺デバイス１１とを具備してなり
、前記中央処理装置からアドレス信号を出力する
ことにより前記周辺デバイスをアクセスすると共
に該周辺デバイスのアドレスを指定するように構
成したコンピユータシステムであつて、 前記システムリセツト端と前記各リセツト入力
端及び前記各リセツト出力端を介して前記中央処
理装置と前記各周辺デバイスとをデージチエーン
接続し、前記各周辺デバイスに各々設けられ、前
記中央処理装置から出力されるアドレス信号に基
づき当該周辺デバイスのアドレスを記憶すると共
に、前記中央処理装置から出力される次のアドレ
ス信号に基づき次段の周辺デバイスのリセツトを
解除する制御回路１２を具備してなるコンピユー
タシステム。[Claims for Utility Model Registration] Central processing unit 10 having a system reset end
and a plurality of peripheral devices 11 each having a reset input terminal and a reset output terminal and connected to the central processing unit via an address bus, and outputting an address signal from the central processing unit. The computer system is configured to access the peripheral device and specify the address of the peripheral device by using the system reset terminal, each of the reset input terminals, and each of the reset output terminals, and the central processing unit. A device that connects each of the peripheral devices in a digital chain, is provided in each of the peripheral devices, stores the address of the peripheral device based on an address signal output from the central processing unit, and outputs the address from the central processing unit. A computer system comprising a control circuit 12 that releases the reset of the next stage peripheral device based on the next address signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2413988U JPH01127045U (en) | 1988-02-25 | 1988-02-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2413988U JPH01127045U (en) | 1988-02-25 | 1988-02-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01127045U true JPH01127045U (en) | 1989-08-30 |
Family
ID=31243730
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2413988U Pending JPH01127045U (en) | 1988-02-25 | 1988-02-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01127045U (en) |
-
1988
- 1988-02-25 JP JP2413988U patent/JPH01127045U/ja active Pending
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