JPH0398535U - - Google Patents
Info
- Publication number
- JPH0398535U JPH0398535U JP807590U JP807590U JPH0398535U JP H0398535 U JPH0398535 U JP H0398535U JP 807590 U JP807590 U JP 807590U JP 807590 U JP807590 U JP 807590U JP H0398535 U JPH0398535 U JP H0398535U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- input terminal
- circuit
- inputs
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000002441 reversible effect Effects 0.000 claims description 3
- 238000006243 chemical reaction Methods 0.000 claims description 2
- 230000000630 rising effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図は、この考案の一実施例を示す図、第２
図は従来のシリアル信号変換装置を示す図である
。
図において１……レジスタ回路、２……変換回
路、３……判定回路、４……可逆カウンタ回路、
５……メモリ回路である。なお、各図中同一符号
は同一又は相当部分を示す。
Figure 1 is a diagram showing an embodiment of this invention;
The figure shows a conventional serial signal converter. In the figure, 1...Register circuit, 2...Conversion circuit, 3...Determination circuit, 4...Reversible counter circuit,
5...Memory circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
パラレル信号を入力し、第２の入力端に、外部か
らのデータ保持信号を入力し、パラレル信号を保
持するレジスタ回路と、入力端に、上記レジスタ
からの出力信号を入力し、信号の種類を判定する
判定回路と、２つの入力端のうち、第１の入力端
には、上記判定回路の出力信号を入力し、上昇又
は下降のカウントをする可逆カウント回路と、２
つの入力端のうち、第１の入力端に、上記可逆カ
ウンタ回路からの出力信号を入力し、第２の入力
端に上記レジスタ回路からの出力信号を入力した
メモリ回路と、２つの入力端のうち、第１の入力
端に、上記メモリ回路の出力信号を入力し、第２
の入力端に、上記メモリ回路からの出力される変
換指示を示す信号を入力し、パラレル信号をシリ
アル信号に変換し、出力するとともに、変換終了
後、変換終了を指示する信号を上記可逆カウンタ
回路のもう一方の入力端に、出力する変換回路か
らなることを、特徴としたシリアル信号変換装置
。 A register circuit that inputs an external parallel signal to the first input terminal of the two input terminals, inputs an external data holding signal to the second input terminal, and holds the parallel signal; A determination circuit inputs the output signal from the register and determines the type of signal, and a first input terminal of the two input terminals inputs the output signal of the determination circuit, and determines whether the signal is rising or falling. a reversible counting circuit that counts 2;
A memory circuit which inputs the output signal from the reversible counter circuit to the first input terminal of the two input terminals, and inputs the output signal from the register circuit to the second input terminal; Of these, the output signal of the memory circuit is input to the first input terminal, and the output signal of the memory circuit is input to the first input terminal.
A signal indicating a conversion instruction outputted from the memory circuit is inputted to the input terminal of the memory circuit, the parallel signal is converted into a serial signal, and the signal is output. A serial signal converter comprising a converter circuit that outputs an output to the other input terminal of the serial signal converter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP807590U JPH0398535U (en) | 1990-01-30 | 1990-01-30 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP807590U JPH0398535U (en) | 1990-01-30 | 1990-01-30 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0398535U true JPH0398535U (en) | 1991-10-14 |
Family
ID=31511719
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP807590U Pending JPH0398535U (en) | 1990-01-30 | 1990-01-30 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0398535U (en) |
-
1990
- 1990-01-30 JP JP807590U patent/JPH0398535U/ja active Pending
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