JPH01169827U - - Google Patents
Info
- Publication number
- JPH01169827U JPH01169827U JP6590188U JP6590188U JPH01169827U JP H01169827 U JPH01169827 U JP H01169827U JP 6590188 U JP6590188 U JP 6590188U JP 6590188 U JP6590188 U JP 6590188U JP H01169827 U JPH01169827 U JP H01169827U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- counter
- terminal
- clock
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Tests Of Electronic Circuits (AREA)
Description
第１図はこの考案の一実施例であるカウンタ回
路のブロツク図、第２図は従来のカウンタ回路の
ブロツク図である。
１ａ……第１カウンタ、１ｂ……第２カウンタ
、２ａ，２ｂ……クロツク端子、３ａ１〜４，３
ｂ１〜４……カウント出力端子、４ａ，４ｂ……
キヤリー信号端子、５ａ，５ｂ……イネーブル信
号端子、６……ＯＲ回路。
FIG. 1 is a block diagram of a counter circuit which is an embodiment of this invention, and FIG. 2 is a block diagram of a conventional counter circuit. 1a...first counter, 1b...second counter, 2a, 2b...clock terminal, 3a 1-4,3
b 1~4 ... Count output terminal, 4a, 4b...
Carry signal terminal, 5a, 5b... Enable signal terminal, 6... OR circuit.
Claims (1)
記クロツク信号の入力回数に応じて信号を出力す
る複数のカウント出力端子と、上記カウント回数
が設定値をオーバーしたときキヤリー信号を出力
するキヤリー信号端子と、イネーブル信号が入力
されるイネーブル信号端子とを有する少なくとも
第１、第２カウンタからなり、第１カウンタのキ
ヤリー信号端子と第２カウンタのイネーブル信号
端子とを接続し、上記カウンタにイネーブル信号
が入力されているときに上記クロツク信号を有効
としてカウントするカウンタ回路において、上記
第１カウンタのキヤリー信号とテスト信号とを入
力し、第２のカウンタのイネーブル信号端子に信
号を出力するＯＲ回路を備えたことを特徴とする
カウンタ回路。 a clock terminal into which a clock signal is input; a plurality of count output terminals which output signals according to the number of times the clock signal is input; and a carry signal terminal which outputs a carry signal when the number of counts exceeds a set value; The carry signal terminal of the first counter is connected to the enable signal terminal of the second counter, and the enable signal is input to the counter. The counter circuit counts the clock signal as valid when the clock signal is active, and includes an OR circuit that inputs the carry signal and the test signal of the first counter and outputs the signal to the enable signal terminal of the second counter. A counter circuit featuring:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6590188U JPH01169827U (en) | 1988-05-19 | 1988-05-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6590188U JPH01169827U (en) | 1988-05-19 | 1988-05-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01169827U true JPH01169827U (en) | 1989-11-30 |
Family
ID=31291322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6590188U Pending JPH01169827U (en) | 1988-05-19 | 1988-05-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01169827U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563434B2 (en) * | 1990-07-10 | 1993-09-10 | Tatsuro Kuratomi |
-
1988
- 1988-05-19 JP JP6590188U patent/JPH01169827U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0563434B2 (en) * | 1990-07-10 | 1993-09-10 | Tatsuro Kuratomi |
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