JPS6422950U - - Google Patents
Info
- Publication number
- JPS6422950U JPS6422950U JP11881287U JP11881287U JPS6422950U JP S6422950 U JPS6422950 U JP S6422950U JP 11881287 U JP11881287 U JP 11881287U JP 11881287 U JP11881287 U JP 11881287U JP S6422950 U JPS6422950 U JP S6422950U
- Authority
- JP
- Japan
- Prior art keywords
- output terminal
- time
- circuit
- reset
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Control For Baths (AREA)
Description
第１図は本考案の一実施例を示す電気回路図、
第２図は同例におけるタイミング図、第３図は同
例におけるブロツク回路図、第４図は従来例のブ
ロツク回路図である。
１……時計制御回路、２１……リセツト回路、
２２……オア回路、２３……フリツプフロツプ回
路、ＨＴＯ……第１の出力端子、ＴＭＯ……第２
の出力端子、ＲＳＴ……リセツト端子。
FIG. 1 is an electrical circuit diagram showing an embodiment of the present invention;
FIG. 2 is a timing diagram of the same example, FIG. 3 is a block circuit diagram of the same example, and FIG. 4 is a block circuit diagram of the conventional example. 1...Clock control circuit, 21...Reset circuit,
22...OR circuit, 23...flip-flop circuit, HTO...first output terminal, TMO...second
output terminal, RST...reset terminal.
Claims (1)
時間にわたり低値信号が出力される第１の出力端
子と、現在時刻と予約時間が一致した時以後一定
の短時間にわたり低値信号が出力される第２の出
力端子と、低値のリセツト信号入力時に前記第１
の出力端子からの出力を高値にリセツトするリセ
ツト端子とを備える時計制御回路を設け、前記第
１の出力端子からの出力を入力して上記所定の短
時間内にリセツト信号を出力するリセツト回路と
、第１の出力端子及び第２の出力端子の出力を入
力するオア回路と、このオア回路の出力端子に接
続されたフリツプフロツプ回路とを設けたことを
特徴とする遠隔制御装置。 The first output terminal outputs a low value signal for a fixed period of time after the current time and the reserved time match, and the first output terminal outputs a low value signal for a fixed short period of time after the current time and the reserved time match. and the first output terminal when a low value reset signal is input.
a reset terminal for resetting the output from the output terminal to a high value; a reset circuit for inputting the output from the first output terminal and outputting a reset signal within the predetermined short time; , an OR circuit that inputs the outputs of a first output terminal and a second output terminal, and a flip-flop circuit connected to the output terminal of the OR circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11881287U JPS6422950U (en) | 1987-07-31 | 1987-07-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11881287U JPS6422950U (en) | 1987-07-31 | 1987-07-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6422950U true JPS6422950U (en) | 1989-02-07 |
Family
ID=31363487
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11881287U Pending JPS6422950U (en) | 1987-07-31 | 1987-07-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6422950U (en) |
-
1987
- 1987-07-31 JP JP11881287U patent/JPS6422950U/ja active Pending
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