JPS63139650U - - Google Patents

Info

Publication number
JPS63139650U
JPS63139650U JP2861687U JP2861687U JPS63139650U JP S63139650 U JPS63139650 U JP S63139650U JP 2861687 U JP2861687 U JP 2861687U JP 2861687 U JP2861687 U JP 2861687U JP S63139650 U JPS63139650 U JP S63139650U
Authority
JP
Japan
Prior art keywords
alarm signal
inputs
microprocessor
signal
outputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2861687U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP2861687U priority Critical patent/JPS63139650U/ja
Publication of JPS63139650U publication Critical patent/JPS63139650U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)
  • Hardware Redundancy (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のマイクロプロセツサの動作監
視回路の構成図、第2図イ,ロ,ハは本考案回路
の動作を表わすタイムチヤートである。 1……マイクロプロセツサ、2……ウオツチ・
ドツグ・タイマ、3……遅延回路、B……バス。
FIG. 1 is a block diagram of an operation monitoring circuit of a microprocessor according to the present invention, and FIG. 2 A, B, and C are time charts showing the operation of the circuit according to the present invention. 1... Microprocessor, 2... Watch.
Dog timer, 3...delay circuit, B...bus.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 後述するマイクロプロセツサから一定時間以上
アクセスがないと警報信号を出力するウオツチ・
ドツグ・タイマと、前記警報信号を入力して遅延
信号を出力する遅延回路と、前記警報信号を最優
先割り込み端子に入力し前記遅延信号をリセツト
端子に入力し前記警報信号と前記遅延信号とに発
生する時間遅れの期間に現在の動作状態をメモリ
に転送するマイクロプロセツサとからなるマイク
ロプロセツサの動作監視回路。
A watch that outputs an alarm signal if there is no access from the microprocessor for a certain period of time (described later)
a dog timer; a delay circuit that inputs the alarm signal and outputs a delayed signal; and inputs the alarm signal to a top priority interrupt terminal and inputs the delayed signal to a reset terminal to output the alarm signal and the delayed signal. A microprocessor operation monitoring circuit consisting of a microprocessor that transfers the current operating state to memory during the time delay period that occurs.
JP2861687U 1987-02-27 1987-02-27 Pending JPS63139650U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2861687U JPS63139650U (en) 1987-02-27 1987-02-27

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2861687U JPS63139650U (en) 1987-02-27 1987-02-27

Publications (1)

Publication Number Publication Date
JPS63139650U true JPS63139650U (en) 1988-09-14

Family

ID=30831747

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2861687U Pending JPS63139650U (en) 1987-02-27 1987-02-27

Country Status (1)

Country Link
JP (1) JPS63139650U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011177390A (en) * 2010-03-02 2011-09-15 Sophia Co Ltd Game machine

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011177390A (en) * 2010-03-02 2011-09-15 Sophia Co Ltd Game machine

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