JPH0250758U - - Google Patents
Info
- Publication number
- JPH0250758U JPH0250758U JP12895788U JP12895788U JPH0250758U JP H0250758 U JPH0250758 U JP H0250758U JP 12895788 U JP12895788 U JP 12895788U JP 12895788 U JP12895788 U JP 12895788U JP H0250758 U JPH0250758 U JP H0250758U
- Authority
- JP
- Japan
- Prior art keywords
- computer
- restart
- dump
- signal
- requesting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
- Retry When Errors Occur (AREA)
Description
第1図は本考案の計算機の再スタート装置を表
わすブロツク図、第2図は本考案装置の動作を表
わすタイムチヤート、第3図は従来の装置を表わ
すブロツク図である。
1……プロセツサ、21〜2n……I/O装置
、3……再スタート装置、31……制御部、31
1……割り込み発生回路、312……フリツプ・
フロツプ回路、313……タイマ、314……リ
セツト回路。
FIG. 1 is a block diagram showing a computer restart device of the present invention, FIG. 2 is a time chart showing the operation of the device of the present invention, and FIG. 3 is a block diagram showing a conventional device. 1...Processor, 21-2n...I/O device, 3...Restart device, 31...Control unit, 31
1...Interrupt generation circuit, 312...Flip
Flop circuit, 313...timer, 314...reset circuit.
Claims (1)
が接続される計算機に設置される計算機の再スタ
ート装置において、前記計算機に再スタートを要
求するスイツチ手段と、この再スタート信号によ
り前記計算機にダンプ開始の割り込みをかけ、ダ
ンプ完了通知を受けた際は通常処理を行い、一定
時間経過して前記プロセツサからダンプ完了通知
が与えられない際はリセツト信号を出力する制御
部とを設けたことを特徴とする計算機の再スター
ト装置。 In a computer restart device installed in a computer to which at least one or more I/O devices are connected across a bus, there is provided a switch means for requesting a restart from the computer, and a switch means for requesting a restart from the computer, and a dump signal to the computer based on the restart signal. A control unit is provided which issues a start interrupt, performs normal processing when a dump completion notification is received, and outputs a reset signal when a dump completion notification is not given from the processor after a certain period of time has elapsed. A device for restarting a computer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12895788U JPH0250758U (en) | 1988-09-30 | 1988-09-30 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12895788U JPH0250758U (en) | 1988-09-30 | 1988-09-30 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0250758U true JPH0250758U (en) | 1990-04-10 |
Family
ID=31382779
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12895788U Pending JPH0250758U (en) | 1988-09-30 | 1988-09-30 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0250758U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007094537A (en) * | 2005-09-27 | 2007-04-12 | Hitachi Ltd | Memory dump device and memory dump collection method |
-
1988
- 1988-09-30 JP JP12895788U patent/JPH0250758U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007094537A (en) * | 2005-09-27 | 2007-04-12 | Hitachi Ltd | Memory dump device and memory dump collection method |
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