JPS63130839U - - Google Patents
Info
- Publication number
- JPS63130839U JPS63130839U JP2347087U JP2347087U JPS63130839U JP S63130839 U JPS63130839 U JP S63130839U JP 2347087 U JP2347087 U JP 2347087U JP 2347087 U JP2347087 U JP 2347087U JP S63130839 U JPS63130839 U JP S63130839U
- Authority
- JP
- Japan
- Prior art keywords
- watchdog timer
- signal
- reset
- reset signal
- timer circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Hardware Redundancy (AREA)
- Debugging And Monitoring (AREA)
Description
第１図は本考案のウオツチドツグタイマ装置の
基本構成を例示するブロツク図、第２図は本考案
一実施例のウオツチドツグタイマ装置の構成を示
すブロツク図、第３図はマイクロコンピユータ１
が実行する「制御メインルーチン」の処理を示す
フローチヤート、第４図は動作例を示すタイミン
グチヤート、第５図は従来のウオツチドツグタイ
マ装置を示すブロツク図、である。
１……マイクロコンピユータ、２……クリア信
号発生回路、３……ウオツチドツグタイマ回路、
１０，１１，１２……信号線。
FIG. 1 is a block diagram illustrating the basic configuration of a watchdog timer device according to the present invention, FIG. 2 is a block diagram illustrating the configuration of a watchdog timer device according to an embodiment of the present invention, and FIG. 3 is a micro computer 1
FIG. 4 is a timing chart showing an example of operation, and FIG. 5 is a block diagram showing a conventional watchdog timer device. 1...Microcomputer, 2...Clear signal generation circuit, 3...Watchdog timer circuit,
10, 11, 12...signal lines.
Claims (1)
ロセツサをリセツトするリセツト信号を出力する
ウオツチドツグタイマ回路を備えたウオツチドツ
グタイマ装置において、 上記プロセツサに、 各々異なる処理内で少なくとも所定時間内に実
行され、セツト信号を出力するセツト信号出力手
段とリセツト信号を出力するリセツト信号出力手
段とを備えると共に、 更に、上記出力されるセツト信号及びリセツト
信号を共に入力することにより上記ウオツチドツ
グタイマ回路の値をクリアするクリア信号を出力
するクリア信号発生回路と、 を備えたことを特徴とするウオツチドツグタイマ
装置。[Claims for Utility Model Registration] In a watchdog timer device comprising a watchdog timer circuit that outputs a reset signal to reset the processor when the processor is not operating normally, It is executed in different processes at least within a predetermined time, and includes a set signal output means for outputting a set signal and a reset signal output means for outputting a reset signal, and further inputs both the set signal and reset signal outputted above. A watchdog timer device comprising: a clear signal generating circuit that outputs a clear signal that clears the value of the watchdog timer circuit by clearing the value of the watchdog timer circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2347087U JPS63130839U (en) | 1987-02-19 | 1987-02-19 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2347087U JPS63130839U (en) | 1987-02-19 | 1987-02-19 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63130839U true JPS63130839U (en) | 1988-08-26 |
Family
ID=30821798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2347087U Pending JPS63130839U (en) | 1987-02-19 | 1987-02-19 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63130839U (en) |
-
1987
- 1987-02-19 JP JP2347087U patent/JPS63130839U/ja active Pending
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