JPS63143949U - - Google Patents
Info
- Publication number
- JPS63143949U JPS63143949U JP3360187U JP3360187U JPS63143949U JP S63143949 U JPS63143949 U JP S63143949U JP 3360187 U JP3360187 U JP 3360187U JP 3360187 U JP3360187 U JP 3360187U JP S63143949 U JPS63143949 U JP S63143949U
- Authority
- JP
- Japan
- Prior art keywords
- watchdog timer
- processor
- outputted
- reset
- reset signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000001052 transient effect Effects 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案一実施例のウオツチドツグタイ
マ装置の構成を示すブロツク図、第２図はマイク
ロプロセツサユニツト５が正常状態の場合のウオ
ツチドツグタイマ装置の動作を示すタイミングチ
ヤート、第３図は同じく一過性の暴走状態の場合
の動作を示すタイミングチヤート、第４図は同じ
く定常的暴走状態の場合の動作を示すタイミング
チヤート、第５図は従来のウオツチドツグタイマ
装置を例示するブロツク図、である。
１…ウオツチドツグタイマ回路、２…発振回路
、３…カウンタ回路、５…マイクロプロセツサユ
ニツト。
FIG. 1 is a block diagram showing the configuration of a watchdog timer device according to an embodiment of the present invention, and FIG. 2 is a timing chart showing the operation of the watchdog timer device when the microprocessor unit 5 is in a normal state. , FIG. 3 is a timing chart showing the operation in a transient runaway state, FIG. 4 is a timing chart showing the operation in a steady runaway state, and FIG. 5 is a conventional watchdog timer. FIG. 3 is a block diagram illustrating the device. DESCRIPTION OF SYMBOLS 1... Watchdog timer circuit, 2... Oscillator circuit, 3... Counter circuit, 5... Microprocessor unit.
Claims (1)
れなかつたとき、該プロセツサをリセツトするリ
セツト信号を出力するウオツチドツグタイマ回路
を備えたウオツチドツグタイマ装置において、 上記ウオツチドツグタイマ回路の出力するリセ
ツト信号が同じ周期で所定回数以上出力されたと
き異常信号を出力する警告手段を備えたことを特
徴とするウオツチドツグタイマ装置。[Claims for Utility Model Registration] A watchdog timer device comprising a watchdog timer circuit that outputs a reset signal to reset the processor when the processor is not accessed within a predetermined time, A watchdog timer device comprising warning means for outputting an abnormality signal when the reset signal outputted by the watchdog timer circuit is outputted a predetermined number of times or more in the same cycle.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3360187U JPS63143949U (en) | 1987-03-06 | 1987-03-06 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3360187U JPS63143949U (en) | 1987-03-06 | 1987-03-06 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63143949U true JPS63143949U (en) | 1988-09-21 |
Family
ID=30841360
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3360187U Pending JPS63143949U (en) | 1987-03-06 | 1987-03-06 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63143949U (en) |
-
1987
- 1987-03-06 JP JP3360187U patent/JPS63143949U/ja active Pending