JPS6327946U - - Google Patents

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Publication number
JPS6327946U
JPS6327946U JP12014386U JP12014386U JPS6327946U JP S6327946 U JPS6327946 U JP S6327946U JP 12014386 U JP12014386 U JP 12014386U JP 12014386 U JP12014386 U JP 12014386U JP S6327946 U JPS6327946 U JP S6327946U
Authority
JP
Japan
Prior art keywords
interrupt
flop
flip
signal
computer system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12014386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP12014386U priority Critical patent/JPS6327946U/ja
Publication of JPS6327946U publication Critical patent/JPS6327946U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案のコンピユータシステム誤動作
検出回路の一実施例の回路図、第2図は第1図の
回路の動作を説明するためのタイミング図である
。 1……RSフリツプフロツプ、2……Dフリツ
プフロツプ、IREQ……割り込み要求信号、I
ACK……割り込み応答信号、ALM……アラー
ム信号。
FIG. 1 is a circuit diagram of an embodiment of the computer system malfunction detection circuit of the present invention, and FIG. 2 is a timing diagram for explaining the operation of the circuit of FIG. 1. 1...RS flip-flop, 2...D flip-flop, IREQ...interrupt request signal, I
ACK...Interrupt response signal, ALM...Alarm signal.

Claims (1)

【実用新案登録請求の範囲】 割り込みを使用しているコンピユータシステム
において、 割り込み要求信号によつてセツトされ、割り込
み応答信号によつてリセツトされるRSフリツプ
フロツプと、 RSフリツプフロツプのQ出力をD入力、割り
込み要求信号をクロツク入力とし、割り込み要求
に対して割り込み処理がなされたか否かを示す信
号をQ出力より出力するDフリツプフロツプとを
有するコンピユータシステム誤動作検出回路。
[Claim for Utility Model Registration] In a computer system that uses interrupts, an RS flip-flop is set by an interrupt request signal and reset by an interrupt response signal, and the Q output of the RS flip-flop is connected to the D input and the interrupt A computer system malfunction detection circuit having a D flip-flop which receives a request signal as a clock input and outputs from a Q output a signal indicating whether or not interrupt processing has been performed in response to an interrupt request.
JP12014386U 1986-08-04 1986-08-04 Pending JPS6327946U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12014386U JPS6327946U (en) 1986-08-04 1986-08-04

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12014386U JPS6327946U (en) 1986-08-04 1986-08-04

Publications (1)

Publication Number Publication Date
JPS6327946U true JPS6327946U (en) 1988-02-24

Family

ID=31008186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12014386U Pending JPS6327946U (en) 1986-08-04 1986-08-04

Country Status (1)

Country Link
JP (1) JPS6327946U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5093358A (en) * 1973-12-19 1975-07-25

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5093358A (en) * 1973-12-19 1975-07-25

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