JPH022706U - - Google Patents
Info
- Publication number
- JPH022706U JPH022706U JP8059688U JP8059688U JPH022706U JP H022706 U JPH022706 U JP H022706U JP 8059688 U JP8059688 U JP 8059688U JP 8059688 U JP8059688 U JP 8059688U JP H022706 U JPH022706 U JP H022706U
- Authority
- JP
- Japan
- Prior art keywords
- data
- pulse
- input
- analog
- digital
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 3
- 238000004088 simulation Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
- Programmable Controllers (AREA)
Description
第１図はこの考案の一実施例のブロツク図、第
２図は上記実施例におけるデータ処理部のパルス
処理動作を説明するフローチヤート、第３図はパ
ルス信号の積算値と瞬時値との関係を示すグラフ
である。
１……プロセス、２……Ｉ／Ｏカード、３……
データバス、４……データ処理部、５……データ
表示・設定器、６……Ｉ／Ｏカード。
Fig. 1 is a block diagram of an embodiment of this invention, Fig. 2 is a flowchart explaining the pulse processing operation of the data processing section in the above embodiment, and Fig. 3 is the relationship between the integrated value and the instantaneous value of the pulse signal. This is a graph showing. 1...process, 2...I/O card, 3...
Data bus, 4...Data processing unit, 5...Data display/setting device, 6...I/O card.
Claims (1)
パルス信号それぞれの入力手段と、プロセスに対
するデジタル信号、アナログ信号それぞれの出力
手段と、前記各入力手段の入力データを処理周期
毎に演算処理するデータ処理手段と、このデータ
処理手段に対してロジツク試験モード時に各デジ
タル入力データ、アナログ入力データ、パルス入
力データ、デジタル出力データ、アナログ出力デ
ータそれぞれを設定するデータ設定手段とを備え
、前記データ処理手段がロジツク試験モード時に
現在瞬時値に登録されているパルスデータを読込
んで処理周期単位のパルス増加量を求め、求めた
パルス増加量を積算して今回積算値を求めて登録
するパルス信号シユミレーシヨン機能を有して成
る入出力データ処理装置。 Digital signals from processes, analog signals,
A means for inputting each pulse signal, a means for outputting a digital signal and an analog signal to the process, a data processing means for processing the input data of each input means for each processing cycle, and a logic test for this data processing means. data setting means for setting each of digital input data, analog input data, pulse input data, digital output data, and analog output data in the logic test mode, and the data processing means is registered in the current instantaneous value in the logic test mode. An input/output data processing device having a pulse signal simulation function that reads pulse data, determines the amount of pulse increase per processing cycle, integrates the determined amount of pulse increase, and calculates and registers the current integrated value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8059688U JPH022706U (en) | 1988-06-20 | 1988-06-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8059688U JPH022706U (en) | 1988-06-20 | 1988-06-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH022706U true JPH022706U (en) | 1990-01-10 |
Family
ID=31305418
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8059688U Pending JPH022706U (en) | 1988-06-20 | 1988-06-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH022706U (en) |
-
1988
- 1988-06-20 JP JP8059688U patent/JPH022706U/ja active Pending