JPH0467751U - - Google Patents
Info
- Publication number
- JPH0467751U JPH0467751U JP10766290U JP10766290U JPH0467751U JP H0467751 U JPH0467751 U JP H0467751U JP 10766290 U JP10766290 U JP 10766290U JP 10766290 U JP10766290 U JP 10766290U JP H0467751 U JPH0467751 U JP H0467751U
- Authority
- JP
- Japan
- Prior art keywords
- watchdog timer
- interrupt
- flip
- processing program
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案のウオツチドツグタイマ制御装
置のブロツク図、第２図は従来のウオツチドツグ
タイマ制御装置のブロツク図、第３図は従来のウ
オツチドツグタイマ制御装置のタイムチヤート、
第４図及び第７図は本考案のウオツチドツグタイ
マ制御装置のタイムチヤート、第５図は本考案の
ウオツチドツグタイマ制御装置の動作フローチヤ
ート、第６図は通知情報の説明図である。
１１……ウオツチドツグタイマ、１２……割り
込み発生回路（フリツプフロツプ）、１３……フ
リツプフロツプ、１４……障害信号発生手段。
Fig. 1 is a block diagram of a watchdog timer control device of the present invention, Fig. 2 is a block diagram of a conventional watchdog timer control device, and Fig. 3 is a time diagram of a conventional watchdog timer control device. Chart,
4 and 7 are time charts of the watchdog timer control device of the present invention, FIG. 5 is an operation flowchart of the watchdog timer control device of the present invention, and FIG. 6 is an explanatory diagram of notification information. It is. 11...watchdog timer, 12...interrupt generation circuit (flip-flop), 13...flip-flop, 14...failure signal generation means.
Claims (1)
で割り込み信号を発生させる割り込み発生回路と
、 前記割り込み信号の発生と同時にセツトされ、
前記割り込みによる処理プログラムとは別の処理
プログラムでリセツトが行なわれる少なくとも一
つ以上のフリツプフロツプと、 前記フリツプフロツプが前記一定周期を超えて
もリセツトされない場合、障害信号を発生させる
障害信号発生手段とを設けたことを特徴とするウ
オツチドツグタイマ制御装置。[Scope of Claim for Utility Model Registration] An interrupt generation circuit that generates an interrupt signal at regular intervals based on the output of a watchdog timer;
At least one or more flip-flops are reset by a processing program different from the interrupt processing program, and a fault signal generating means is provided for generating a fault signal when the flip-flop is not reset even after the predetermined period. A watchdog timer control device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10766290U JPH0467751U (en) | 1990-10-16 | 1990-10-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10766290U JPH0467751U (en) | 1990-10-16 | 1990-10-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0467751U true JPH0467751U (en) | 1992-06-16 |
Family
ID=31854296
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10766290U Pending JPH0467751U (en) | 1990-10-16 | 1990-10-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0467751U (en) |
-
1990
- 1990-10-16 JP JP10766290U patent/JPH0467751U/ja active Pending
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