JPH022748U - - Google Patents
Info
- Publication number
- JPH022748U JPH022748U JP7706788U JP7706788U JPH022748U JP H022748 U JPH022748 U JP H022748U JP 7706788 U JP7706788 U JP 7706788U JP 7706788 U JP7706788 U JP 7706788U JP H022748 U JPH022748 U JP H022748U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- cpu
- sending
- abnormality detection
- abnormality
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims description 7
- 238000001514 detection method Methods 0.000 claims description 5
- 230000002159 abnormal effect Effects 0.000 claims 2
- 238000012790 confirmation Methods 0.000 claims 1
- 230000007257 malfunction Effects 0.000 claims 1
- 238000012806 monitoring device Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Description
第１図はこの考案の実施例を示すブロツク図、
第２図は上記実施例の比較手段を示す回路図、第
３図は上記実施例のリセツト手段を示す回路図、
第４図は上記実施例の異常検出手段を示す回路図
、第５図は上記実施例の動作を示すフローチヤー
ト、第６図は比較手段の動作を示す波形図である
。
１，２……ＣＰＵ、３……発振器、４……比較
手段、５……セレクト手段、６……リセツト手段
、７……異常検出手段。
Figure 1 is a block diagram showing an embodiment of this invention.
FIG. 2 is a circuit diagram showing the comparison means of the above embodiment, FIG. 3 is a circuit diagram showing the reset means of the above embodiment,
FIG. 4 is a circuit diagram showing the abnormality detection means of the above embodiment, FIG. 5 is a flowchart showing the operation of the above embodiment, and FIG. 6 is a waveform diagram showing the operation of the comparison means. 1, 2... CPU, 3... Oscillator, 4... Comparison means, 5... Selecting means, 6... Resetting means, 7... Abnormality detection means.
Claims (1)
から送られる制御信号の確定信号を受けて各ＣＰ
Ｕから出力される制御信号の異同を比較し、各Ｃ
ＰＵの制御信号が異なつたときに異常信号を送り
出す比較手段と、 該比較手段からの異常信号を受けて各ＣＰＵに
再起動を行うリセツト信号を送るリセツト手段と
、 上記比較手段から各ＣＰＵの再起動後の異常信
号を受けてＣＰＵの異常検出信号を送り出す異常
検出手段と、 上記比較手段から送られる異常信号を選択して
上記リセツト手段と異常検出手段とに送るセレク
ト手段と、 を備えたことを特徴とするＣＰＵの誤動作監視装
置。[Claims for Utility Model Registration] Each CPU receives a confirmation signal of a control signal sent from any one of a plurality of CPUs having the same function.
By comparing the control signals output from U, each C
Comparing means for sending out an abnormal signal when the control signal of the PU is different; Resetting means for sending a reset signal for restarting each CPU in response to the abnormal signal from the comparing means; Abnormality detection means for receiving an abnormality signal after startup and sending out a CPU abnormality detection signal; and selection means for selecting the abnormality signal sent from the comparison means and sending it to the reset means and the abnormality detection means. A CPU malfunction monitoring device characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7706788U JPH022748U (en) | 1988-06-10 | 1988-06-10 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7706788U JPH022748U (en) | 1988-06-10 | 1988-06-10 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH022748U true JPH022748U (en) | 1990-01-10 |
Family
ID=31302068
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7706788U Pending JPH022748U (en) | 1988-06-10 | 1988-06-10 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH022748U (en) |
-
1988
- 1988-06-10 JP JP7706788U patent/JPH022748U/ja active Pending