JPS643961U - - Google Patents
Info
- Publication number
- JPS643961U JPS643961U JP9671187U JP9671187U JPS643961U JP S643961 U JPS643961 U JP S643961U JP 9671187 U JP9671187 U JP 9671187U JP 9671187 U JP9671187 U JP 9671187U JP S643961 U JPS643961 U JP S643961U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- time
- timer
- output
- gate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims 1
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は、本考案の一実施例を示す構成ブロツ
ク図、第２図は第１図の装置の動作を説明する波
形図である。第３図は従来のウオツチドツグタイ
マの構成ブロツク図、第４図は第３図の装置の信
号波形図である。
１２，１３…タイマ、２０，３０…ゲート回路
、ＣＬＫ…基準クロツク、ＥＲＲＯＲ…エラー信
号、ＲＥＳＥＴ…リセツト信号。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a waveform diagram illustrating the operation of the device shown in FIG. FIG. 3 is a block diagram of a conventional watchdog timer, and FIG. 4 is a signal waveform diagram of the device shown in FIG. 12, 13...Timer, 20, 30...Gate circuit, CLK...Reference clock, ERROR...Error signal, RESET...Reset signal.
Claims (1)
るＭＰＵシステムに対して、このＭＰＵシステム
が一定の時間内にこのリセツト信号を出力しない
場合はタイムアツプしてエラー信号を出力するウ
オツチドツグタイマにおいて、 前記定周期より短い定時間（Ｔ１）でタイムア
ツプする第１のタイマ、 前記定周期より長い定時間（Ｔ２）でタイムア
ツプする第２のタイマ、 当該第１のタイマのタイムアツプ信号と前記リ
セツト信号を入力し、前記リセツト受信時にこの
タイムアツプ信号が出力されていない場合に異常
検出信号を出力する第１のゲート、 この第１のゲートの出力する異常検出信号と当
該第２のタイマの出力するタイムアツプ信号との
論理和をとつて前記エラー信号として出力する第
２のゲート、 よりなることを特徴とするウオツチドツグタイ
マ。[Claim for Utility Model Registration] For an MPU system that outputs a reset signal at a predetermined regular cycle (T0), if this MPU system does not output this reset signal within a certain period of time, it will time up and issue an error signal. Among the watchdog timers that output, a first timer that times up at a fixed time (T1) shorter than the fixed cycle, a second timer that times up at a fixed time (T2) longer than the fixed cycle, and the first timer. a first gate that inputs the time-up signal of the first gate and the reset signal and outputs an abnormality detection signal if the time-up signal is not output when the reset is received; 1. A watchdog timer comprising: a second gate that performs a logical sum with a time-up signal output from a second timer and outputs the result as the error signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9671187U JPS643961U (en) | 1987-06-24 | 1987-06-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9671187U JPS643961U (en) | 1987-06-24 | 1987-06-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS643961U true JPS643961U (en) | 1989-01-11 |
Family
ID=31321789
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9671187U Pending JPS643961U (en) | 1987-06-24 | 1987-06-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS643961U (en) |
-
1987
- 1987-06-24 JP JP9671187U patent/JPS643961U/ja active Pending
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