JPH01123251U - - Google Patents
Info
- Publication number
- JPH01123251U JPH01123251U JP1834088U JP1834088U JPH01123251U JP H01123251 U JPH01123251 U JP H01123251U JP 1834088 U JP1834088 U JP 1834088U JP 1834088 U JP1834088 U JP 1834088U JP H01123251 U JPH01123251 U JP H01123251U
- Authority
- JP
- Japan
- Prior art keywords
- oscillation
- microprocessor
- binary signal
- command state
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010355 oscillation Effects 0.000 claims description 10
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案の一実施例の構成図、第２図は
第１図における要部の波形説明図、第３図は従来
のウオツチドツグタイマ回路の構成図、第４図は
第３図における要部の波形説明図である。
１，２……ウオツチドツグタイマ回路、Ｐａ…
…発振停止信号、Ｖ４ｃ……二値信号、Ｑ６……
マイクロプロセツサ、ＲＳ……リセツト端子。
Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a waveform explanatory diagram of the main parts in Fig. 1, Fig. 3 is a block diagram of a conventional watchdog timer circuit, and Fig. 4 is a block diagram of a conventional watchdog timer circuit. FIG. 3 is a waveform explanatory diagram of the main part in FIG. 3; 1, 2...Watchdog timer circuit, Pa...
...Oscillation stop signal, V 4c ... Binary signal, Q 6 ...
Microprocessor, RS...Reset terminal.
Claims (1)
とリセツト指令状態とが交互にかつ周期的に繰り
返される二値信号を出力する発振動作を行い、か
つ前記発振停止信号が入力されると前記二値信号
を前記リセツト指令状態にし、かつ複数個の前記
発振停止信号が引き続いて入力された場合に相隣
る二個の前記発信停止信号間の時間間隔がすべて
所定時間未満であると前記発振動作を停止して前
記二値信号を前記セツト指令状態に保持し、かつ
前記時間間隔が前記所定時間以上になると前記発
振動作を再開するものであつて、前記二値信号を
マイクロプロセツサのリセツト端子に入力される
信号とし、かつ前記発振停止信号を前記マイクロ
プロセツサから出力される信号とし、かつ前記リ
セツト端子に入力された前記二値信号が前記リセ
ツト指令状態になると前記マイクロプロセツサが
初期状態になつて待機し前記二値信号が前記セツ
ト指令状態になると前記マイクロプロセツサが歩
進動作を開始するように前記マイクロプロセツサ
を構成することによつて、前記マイクロプロセツ
サの前記歩進動作を前記発振動作を介して監視す
ることを特徴とするウオツチドツグタイマ回路。 When the oscillation stop signal is not input, an oscillation operation is performed that outputs a binary signal in which the set command state and the reset command state are alternately and periodically repeated, and when the oscillation stop signal is input, the binary signal is output. When the reset command state is set and a plurality of the oscillation stop signals are input successively, the oscillation operation is stopped if the time intervals between two adjacent oscillation stop signals are all less than a predetermined time. and maintains the binary signal in the set command state, and resumes the oscillation operation when the time interval exceeds the predetermined time, and the binary signal is input to the reset terminal of the microprocessor. and the oscillation stop signal is a signal output from the microprocessor, and when the binary signal input to the reset terminal enters the reset command state, the microprocessor enters the initial state. The step operation of the microprocessor is controlled by the oscillation by configuring the microprocessor so that when the binary signal reaches the set command state, the microprocessor starts the step operation. A watchdog timer circuit characterized by monitoring through operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1834088U JPH01123251U (en) | 1988-02-15 | 1988-02-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1834088U JPH01123251U (en) | 1988-02-15 | 1988-02-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01123251U true JPH01123251U (en) | 1989-08-22 |
Family
ID=31232898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1834088U Pending JPH01123251U (en) | 1988-02-15 | 1988-02-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01123251U (en) |
-
1988
- 1988-02-15 JP JP1834088U patent/JPH01123251U/ja active Pending