JPH0196044U - - Google Patents
Info
- Publication number
- JPH0196044U JPH0196044U JP19030587U JP19030587U JPH0196044U JP H0196044 U JPH0196044 U JP H0196044U JP 19030587 U JP19030587 U JP 19030587U JP 19030587 U JP19030587 U JP 19030587U JP H0196044 U JPH0196044 U JP H0196044U
- Authority
- JP
- Japan
- Prior art keywords
- abnormality
- arithmetic circuit
- reset
- signal
- digital arithmetic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 9
- 230000005856 abnormality Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案の一実施例を示す回路図、第２
図は第１図における故障信号監視タイマの入出力
波形図、第３図は従来の異常監視回路図である。
１…デイジタル演算回路、２…オアゲート、３
…リセツト監視タイマ、４…故障信号監視タイマ
。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
The figure is an input/output waveform diagram of the failure signal monitoring timer in FIG. 1, and FIG. 3 is a diagram of a conventional abnormality monitoring circuit. 1... Digital arithmetic circuit, 2... OR gate, 3
...Reset monitoring timer, 4...Failure signal monitoring timer.
Claims (1)
のリセツト信号及び故障信号から異常検出を行う
異常監視回路において、前記リセツト信号が所定
時間以上継続したことで異常検出を行うリセツト
監視タイマと、前記故障信号をオン・オフの繰り
返しの正常状態からオン又はオフの状態に変える
デイジタル演算回路と、このデイジタル演算回路
の故障信号がオン・オフの繰り返し停止で異常検
出を行う故障信号監視タイマとを備えたことを特
徴とするデイジタル演算回路の異常監視回路。 An abnormality monitoring circuit that detects an abnormality from a reset signal and a failure signal of a digital arithmetic circuit that performs digital protection calculation includes a reset monitoring timer that detects an abnormality when the reset signal continues for a predetermined period or more, and a reset monitoring timer that turns on the failure signal. It is characterized by comprising a digital arithmetic circuit that changes from a normal state of repeated OFF to an ON or OFF state, and a fault signal monitoring timer that detects an abnormality when a fault signal of this digital arithmetic circuit stops repeatedly turning on and off. Abnormality monitoring circuit for digital arithmetic circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19030587U JPH0196044U (en) | 1987-12-15 | 1987-12-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19030587U JPH0196044U (en) | 1987-12-15 | 1987-12-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0196044U true JPH0196044U (en) | 1989-06-26 |
Family
ID=31481290
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19030587U Pending JPH0196044U (en) | 1987-12-15 | 1987-12-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0196044U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5784369A (en) * | 1980-11-14 | 1982-05-26 | Fuji Electric Co Ltd | Abnormality detecting system for circuit device |
| JPS6211947A (en) * | 1985-07-10 | 1987-01-20 | Fuji Electric Co Ltd | Detecting circuit for program runaway of microcomputer |
-
1987
- 1987-12-15 JP JP19030587U patent/JPH0196044U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5784369A (en) * | 1980-11-14 | 1982-05-26 | Fuji Electric Co Ltd | Abnormality detecting system for circuit device |
| JPS6211947A (en) * | 1985-07-10 | 1987-01-20 | Fuji Electric Co Ltd | Detecting circuit for program runaway of microcomputer |