JPS6289041U - - Google Patents
Info
- Publication number
- JPS6289041U JPS6289041U JP17893785U JP17893785U JPS6289041U JP S6289041 U JPS6289041 U JP S6289041U JP 17893785 U JP17893785 U JP 17893785U JP 17893785 U JP17893785 U JP 17893785U JP S6289041 U JPS6289041 U JP S6289041U
- Authority
- JP
- Japan
- Prior art keywords
- microcomputer
- task
- output
- circuit
- timer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
- Hardware Redundancy (AREA)
Description
第１図は本考案を適用したマイクロコンピユー
タシステムの複数のタスクの構成を示すブロツク
図、第２図は本考案に適用したマイクロコンピユ
ータシステムの故障検出のために備えた回路部分
の構成図である。
１……ＭＰＵ、２……バツフア、３，４，５，
６……カウンタ、７，８，９，１０……パルス発
生回路、１１……論理和回路、１２……警報出力
回路。
Fig. 1 is a block diagram showing the configuration of multiple tasks in a microcomputer system to which the present invention is applied, and Fig. 2 is a block diagram of a circuit section provided for fault detection in the microcomputer system to which the present invention is applied. . 1...MPU, 2...Batsuhua, 3, 4, 5,
6... Counter, 7, 8, 9, 10... Pulse generation circuit, 11... OR circuit, 12... Alarm output circuit.
Claims (1)
、リセツトパルス発生処理を内蔵するとともに、
マイクロコンピユータの外部には各タスクに応じ
たタイマ時間を有するウオツチドツグタイマと、
これらタイマのタイムアツプ出力の論理和を得る
論理和回路を設け、この論理和出力を故障検出出
力とすることを特徴とするマイクロコンピユータ
システム。 Each task of the microcomputer has built-in reset pulse generation processing,
External to the microcomputer is a watchdog timer that has a timer time corresponding to each task.
A microcomputer system characterized by providing an OR circuit for obtaining the OR of time-up outputs of these timers, and using this OR output as a failure detection output.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17893785U JPS6289041U (en) | 1985-11-20 | 1985-11-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17893785U JPS6289041U (en) | 1985-11-20 | 1985-11-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6289041U true JPS6289041U (en) | 1987-06-06 |
Family
ID=31121539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17893785U Pending JPS6289041U (en) | 1985-11-20 | 1985-11-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6289041U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010111068A (en) * | 2008-11-07 | 2010-05-20 | Seiko Epson Corp | Motor control device, recording device and motor control method |
-
1985
- 1985-11-20 JP JP17893785U patent/JPS6289041U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2010111068A (en) * | 2008-11-07 | 2010-05-20 | Seiko Epson Corp | Motor control device, recording device and motor control method |