JPH01164549U - - Google Patents
Info
- Publication number
- JPH01164549U JPH01164549U JP6185988U JP6185988U JPH01164549U JP H01164549 U JPH01164549 U JP H01164549U JP 6185988 U JP6185988 U JP 6185988U JP 6185988 U JP6185988 U JP 6185988U JP H01164549 U JPH01164549 U JP H01164549U
- Authority
- JP
- Japan
- Prior art keywords
- starts
- access
- short
- microprocessor
- long
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims 3
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案を実施したマイクロプロセツサ
監視回路の構成を表わす図、第２図は本考案回路
の動作を表わすフローチヤートである。
１…マイクロプロセツサ、２…通信Ｉ／Ｆ、３
…短時間タイマ、４…長時間タイマ、５…選択回
路、６…オア回路、７…アドレス・デコーダ、Ｓ
Ｂ…システム・バス、ａ１，ａ２，ａ３…アンド
回路。
FIG. 1 is a diagram showing the configuration of a microprocessor monitoring circuit embodying the present invention, and FIG. 2 is a flowchart showing the operation of the circuit according to the present invention. 1...Microprocessor, 2...Communication I/F, 3
... Short time timer, 4... Long time timer, 5... Selection circuit, 6... OR circuit, 7... Address decoder, S
B...System bus, a1, a2, a3...AND circuit.
Claims (1)
エア・リセツトをかけるマイクロプロセツサ監視
回路において、Ｉ／Ｏアクセスの際に起動する短
時間タイマと、Ｉ／Ｏアクセスなしの際に起動す
る長時間タイマと、Ｉ／Ｏアクセスなしの状態で
アドレス・バス上にＩ／Ｏアドレスが送出された
ことを検出する検出手段と、前記短時間タイマが
タイム・アツプした場合、前記長時間タイマがタ
イム・アツプした場合または前記検出手段から検
出出力が出力された場合にハードウエア・リセツ
トを出力するゲート回路とを有するマイクロプロ
セツサ監視回路。 In the microprocessor monitoring circuit that monitors the operation of the microprocessor and performs a hardware reset, there are two types of timers: a short-time timer that starts when an I/O is accessed, and a long-time timer that starts when there is no I/O access. , detection means for detecting that an I/O address is sent on the address bus in a state where there is no I/O access; and when the short timer times up, the long timer times out. and a gate circuit that outputs a hardware reset when a detection output is output from the detection means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6185988U JPH01164549U (en) | 1988-05-11 | 1988-05-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6185988U JPH01164549U (en) | 1988-05-11 | 1988-05-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01164549U true JPH01164549U (en) | 1989-11-16 |
Family
ID=31287505
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6185988U Pending JPH01164549U (en) | 1988-05-11 | 1988-05-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01164549U (en) |
-
1988
- 1988-05-11 JP JP6185988U patent/JPH01164549U/ja active Pending