JPH03127938U - - Google Patents

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Publication number
JPH03127938U
JPH03127938U JP3564390U JP3564390U JPH03127938U JP H03127938 U JPH03127938 U JP H03127938U JP 3564390 U JP3564390 U JP 3564390U JP 3564390 U JP3564390 U JP 3564390U JP H03127938 U JPH03127938 U JP H03127938U
Authority
JP
Japan
Prior art keywords
terminal
cpu
voltage detection
reset
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3564390U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3564390U priority Critical patent/JPH03127938U/ja
Publication of JPH03127938U publication Critical patent/JPH03127938U/ja
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案のCPU監視回路の一実施例で
ある回路図である。第2図は第1図CPU監視回
路の特定点の波形図である。 1…PU、2…電圧検出IC、3…スイツチン
グ回路、4…ロジツク回路、5…リセツト信号引
き延ばし回路、CI…コンデンサ。
FIG. 1 is a circuit diagram showing an embodiment of the CPU monitoring circuit of the present invention. FIG. 2 is a waveform diagram of a specific point of the CPU monitoring circuit of FIG. 1. 1...PU, 2...Voltage detection IC, 3...Switching circuit, 4...Logic circuit, 5...Reset signal extension circuit, CI...Capacitor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] CPUに電源を供給する正極端子にスイツチン
グ回路を介し、コンデンサの一端と電圧検出回路
の電圧検知端子とをそれぞれ接続し、前記コンデ
ンサの他端と電圧検出回路の負極側の端子は負極
端子に接続し、電圧検出回路の出力端子はCPU
のリセツト端子に接続し、ウオツチドツグ・タイ
マクリア端子としてリセツト中は入力状態、リセ
ツト解除後は出力状態となる前記CPUのクリア
端子を使用し、このクリア端子が入力中又はパル
ス制御中はオン、CPU動作異常による単なる出
力中はオフとなるように前記スイツチング回路を
制御するジクロツ回路を前記クリア端子に接続し
て構成することにより、パワーオン・リセツト機
能とウオツチドツグ・タイマリセツト機能とを果
たすことを特徴としたCPU監視回路。
One end of the capacitor and the voltage detection terminal of the voltage detection circuit are each connected to the positive terminal that supplies power to the CPU via a switching circuit, and the other end of the capacitor and the negative terminal of the voltage detection circuit are connected to the negative terminal. The output terminal of the voltage detection circuit is
The CPU's clear terminal is connected to the reset terminal of the CPU and is in the input state during reset and output state after reset is used as the watchdog timer clear terminal.When this clear terminal is inputting or under pulse control, it is turned on and the CPU A power-on reset function and a watchdog timer reset function are achieved by connecting a logic circuit to the clear terminal to control the switching circuit so that it is turned off during mere output due to an operational abnormality. CPU monitoring circuit.
JP3564390U 1990-04-02 1990-04-02 Pending JPH03127938U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3564390U JPH03127938U (en) 1990-04-02 1990-04-02

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3564390U JPH03127938U (en) 1990-04-02 1990-04-02

Publications (1)

Publication Number Publication Date
JPH03127938U true JPH03127938U (en) 1991-12-24

Family

ID=31541178

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3564390U Pending JPH03127938U (en) 1990-04-02 1990-04-02

Country Status (1)

Country Link
JP (1) JPH03127938U (en)

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