JPS61113490U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1... Main control device, 2... Pulse generation circuit, 3
...Checkable state determination circuit, 4...Delay circuit, 5...Controlled device, 6...Pulse width/interval check circuit, 10...Gate.

Claims (1)

[Scope of utility model registration request] A device for detecting the control mode of a system in which when the control mode of the controlled device is remote, the controlled device operates in response to a command from a control device, and when the control mode is local, the controlled device operates independently regardless of the command. a circuit that generates a predetermined pulse signal; a circuit that determines whether the controlled device is operating or non-operating based on a status signal of the controlled device; and a circuit that generates the pulse signal only when the controlled device is not operating. a gate circuit that allows the gate pulse to pass through and outputs it as a gate pulse; a time delay circuit that applies a time delay to the gate pulse and outputs it as a delayed pulse; a first switch that directs the gate pulse to the controlled device when in the remote mode as a command; and a second switch that sends the delayed pulse to the controlled device when in the remote mode as a second command for canceling the first command. A second switch that leads to a control device and outputs a remote detection signal when the pulse width and pulse interval of the status signal of the controlled device corresponding to the gate pulse and the delayed pulse are within a predetermined range, and are not within that range. 1. A control mode detection device comprising: a circuit that outputs a local detection signal when the control mode is detected.