JPS61185144U - - Google Patents
Info
- Publication number
- JPS61185144U JPS61185144U JP5418986U JP5418986U JPS61185144U JP S61185144 U JPS61185144 U JP S61185144U JP 5418986 U JP5418986 U JP 5418986U JP 5418986 U JP5418986 U JP 5418986U JP S61185144 U JPS61185144 U JP S61185144U
- Authority
- JP
- Japan
- Prior art keywords
- microprocessor
- signal
- reset
- output
- supplying
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000002265 prevention Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 3
- 238000012544 monitoring process Methods 0.000 description 1
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図ａ，ｂは本考案の実施例の構成を示す説
明図と部分変形説明図、第２図ａ，ｂは本考案の
他の実施例の構成を示す説明図とその具体回路例
であり、図中、１はマイクロプロセツサ（ＭＰＵ
）、２はアドレスデコーダ、３はラツチ回路、４
，６はＯＲ回路、５はＤ形フリツプフロツプ、７
はリセツトパルス発生回路、１０は１チツプＭＰ
Ｕ、１１は目的回路、１２は論理監視回路を示す
。
Figures 1a and b are explanatory diagrams and partially modified explanatory diagrams showing the configuration of an embodiment of the present invention, and Figures 2a and b are explanatory diagrams showing the configuration of another embodiment of the present invention and its specific circuit example. In the figure, 1 is a microprocessor (MPU).
), 2 is an address decoder, 3 is a latch circuit, 4
, 6 is an OR circuit, 5 is a D-type flip-flop, 7
is a reset pulse generation circuit, 10 is 1 chip MP
U, 11 indicates a target circuit, and 12 indicates a logic monitoring circuit.
Claims (1)
かじめ定められた信号を供給して動作し、リセツ
ト信号が供給されることにより動作状態がリセツ
トされるマイクロプロセツサの暴走防止回路にお
いて、 該マイクロプロセツグの出力線の信号状態があ
らかじめ設定された出力信号か否かを監視する手
段を設け、使用中以外の出力線上に該設定の状態
と異なる出力信号レベルが現われるときマイクロ
プロセツサに対しリセツト信号を発生することを
特徴とするマイクロプロセツサ暴走防止回路。[Claims for Utility Model Registration] Runaway prevention of a microprocessor that operates by supplying a predetermined signal to an output signal line according to a predetermined program, and whose operating state is reset by supplying a reset signal. In the circuit, means is provided to monitor whether the signal state of the output line of the microprocessor is a preset output signal, and when an output signal level different from the set state appears on an output line other than the one in use, the microprocessor A microprocessor runaway prevention circuit characterized by generating a reset signal to a processor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5418986U JPS6213153Y2 (en) | 1986-04-11 | 1986-04-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5418986U JPS6213153Y2 (en) | 1986-04-11 | 1986-04-11 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS61185144U true JPS61185144U (en) | 1986-11-18 |
| JPS6213153Y2 JPS6213153Y2 (en) | 1987-04-04 |
Family
ID=30575725
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5418986U Expired JPS6213153Y2 (en) | 1986-04-11 | 1986-04-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6213153Y2 (en) |
-
1986
- 1986-04-11 JP JP5418986U patent/JPS6213153Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6213153Y2 (en) | 1987-04-04 |
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