JPH01164548U - - Google Patents
Info
- Publication number
- JPH01164548U JPH01164548U JP6176288U JP6176288U JPH01164548U JP H01164548 U JPH01164548 U JP H01164548U JP 6176288 U JP6176288 U JP 6176288U JP 6176288 U JP6176288 U JP 6176288U JP H01164548 U JPH01164548 U JP H01164548U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- input
- group
- outputs
- ports
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims description 6
- 230000005856 abnormality Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Debugging And Monitoring (AREA)
Description
第１図は本考案に係るＣＰＵ動作異常監視回路
の一実施例を示すブロツク構成図、第２図は従来
のＣＰＵ動作異常監視回路のブロツク図である。
１…出力ポート群、２…ｎ入力ＡＮＤ回路、３
…監視用タイマ、４…警報回路、５…ＣＰＵ、６
…データバス、７…ＮＯＴ回路群（０〜ｎ個）。
FIG. 1 is a block diagram showing an embodiment of a CPU operation abnormality monitoring circuit according to the present invention, and FIG. 2 is a block diagram of a conventional CPU operation abnormality monitoring circuit. 1...Output port group, 2...n input AND circuit, 3
...Monitoring timer, 4...Alarm circuit, 5...CPU, 6
...Data bus, 7...NOT circuit group (0 to n pieces).
Claims (1)
ムにおいて、ｎ個の出力ポートと、該ｎ個の出力
ポートに接続された０〜ｎ個のＮＯＴ回路群と、
該０〜ｎ個のＮＯＴ回路群の出力を入力するｎ入
力ＡＮＤ回路と、該ｎ入力ＡＮＤ回路に接続され
た監視用タイマと、該監視用タイマの出力を入力
とする警報回路と、前記出力ポート群に一定周期
で特定の論理の組合せを持つたパルス群を出力す
るソフトウエアとを持つことを特徴とするＣＰＵ
動作異常監視回路。 In a system controlled by a microcomputer, n output ports, 0 to n NOT circuit groups connected to the n output ports,
an n-input AND circuit to which the outputs of the 0 to n NOT circuit groups are input; a monitoring timer connected to the n-input AND circuit; an alarm circuit to which the output of the monitoring timer is input; A CPU characterized by having software that outputs a group of pulses having a specific logic combination to a group of ports at a constant period.
Operation abnormality monitoring circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6176288U JPH01164548U (en) | 1988-05-11 | 1988-05-11 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6176288U JPH01164548U (en) | 1988-05-11 | 1988-05-11 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01164548U true JPH01164548U (en) | 1989-11-16 |
Family
ID=31287410
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6176288U Pending JPH01164548U (en) | 1988-05-11 | 1988-05-11 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01164548U (en) |
-
1988
- 1988-05-11 JP JP6176288U patent/JPH01164548U/ja active Pending
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