JPH0324737U - - Google Patents
Info
- Publication number
- JPH0324737U JPH0324737U JP13826189U JP13826189U JPH0324737U JP H0324737 U JPH0324737 U JP H0324737U JP 13826189 U JP13826189 U JP 13826189U JP 13826189 U JP13826189 U JP 13826189U JP H0324737 U JPH0324737 U JP H0324737U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- data
- outputs
- interrupt
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000004069 differentiation Effects 0.000 claims 1
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 3
Description
第１図は本考案の一実施例を示すブロツク図、
第２図ａ〜ｃは第１図に示すシリアルデータ受信
制御回路の入出力信号の波形図、第３図は従来の
一例を示すブロツク図である。
１……データ受信回路、２……シリアルデータ
デコーダ、３……ＣＰＵ、４……微分回路、５…
…割り込み発生回路、ａ１……変調信号、ａ２…
…データ信号、ａ３……データ、ｂ１……制御信
号、ｃ１〜ｃｎ……割り込み信号、Ｐ０……入力
ポート。
FIG. 1 is a block diagram showing an embodiment of the present invention.
2a to 2c are waveform diagrams of input and output signals of the serial data reception control circuit shown in FIG. 1, and FIG. 3 is a block diagram showing a conventional example. 1...Data receiving circuit, 2...Serial data decoder, 3...CPU, 4...Differential circuit, 5...
...Interrupt generation circuit, a1...Modulation signal, a2...
...Data signal, a3...Data, b1...Control signal, c1-cn...Interrupt signal, P0...Input port.
Claims (1)
調信号を受信し復調して前記データ信号を出力す
るデータ受信回路と、前記データ信号を解読しデ
ータとして出力するシリアルデータデコーダと、
前記変調信号を受信し微分して前記制御信号を出
力する微分回路と、前記制御信号の周波数に応じ
て複数の割り込み信号のうち一つの割り込み信号
を選択出力する割り込み信号発生回路と、前記デ
ータを入力処理すると共に前記割り込み信号を入
力し割り込み処理を行うＣＰＵとを含む事を特徴
とするシリアルデータ受信制御回路。 a data receiving circuit that receives and demodulates a modulated signal modulated by superimposing a control signal on a data signal, and outputs the data signal; a serial data decoder that decodes the data signal and outputs it as data;
a differentiation circuit that receives and differentiates the modulation signal and outputs the control signal; an interrupt signal generation circuit that selects and outputs one of a plurality of interrupt signals according to the frequency of the control signal; A serial data reception control circuit comprising: a CPU that performs input processing, inputs the interrupt signal, and performs interrupt processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13826189U JPH0324737U (en) | 1988-12-07 | 1989-11-28 |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15961988 | 1988-12-07 | ||
| JP13826189U JPH0324737U (en) | 1988-12-07 | 1989-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0324737U true JPH0324737U (en) | 1991-03-14 |
Family
ID=31718987
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13826189U Pending JPH0324737U (en) | 1988-12-07 | 1989-11-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0324737U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003088287A (en) * | 2001-09-14 | 2003-03-25 | Shimano Inc | Hook for stringer and stringer using the same |
-
1989
- 1989-11-28 JP JP13826189U patent/JPH0324737U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003088287A (en) * | 2001-09-14 | 2003-03-25 | Shimano Inc | Hook for stringer and stringer using the same |
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