JPH0164744U

JPH0164744U -

Info

Publication number: JPH0164744U
Application number: JP1987160917U
Authority: JP
Priority date: 1987-10-21
Filing date: 1987-10-21
Publication date: 1989-04-25

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例によるプログラム
制御装置を示す構成図、第２図はそのコマンド要
求手順を示すフローチヤート、第３図は従来のプ
ログラム制御装置を示す構成図である。図において、１はコマンド信号入力、２はコマ
ンド受信回路、３は割り込み信号、４はコマンド
デコード信号、５はデータバス、６はＨＯＬＤ信
号、７はマイクロプロセツサ、８はセレクト信号
、９はセレクト回路、１０はＲＯＭイネーブル信
号、１１はＲＯＭ、１２はＲＡＭイネーブル信号
、１３は第１のＲＡＭ、１４はアドレスカウンタ
イネーブル信号、１５はアドレスカウンタ、１６
はアドレスバス、１７はプログラム書き込み信号
、１８は第２のＲＡＭ、１９は制御回路である。
なお、図中、同一符号は同一、又は相当部分を示
す。 FIG. 1 is a block diagram showing a program control device according to an embodiment of this invention, FIG. 2 is a flowchart showing its command request procedure, and FIG. 3 is a block diagram showing a conventional program control device. In the figure, 1 is a command signal input, 2 is a command receiving circuit, 3 is an interrupt signal, 4 is a command decode signal, 5 is a data bus, 6 is a HOLD signal, 7 is a microprocessor, 8 is a select signal, and 9 is a select signal. circuit, 10 is a ROM enable signal, 11 is a ROM, 12 is a RAM enable signal, 13 is a first RAM, 14 is an address counter enable signal, 15 is an address counter, 16
17 is an address bus, 17 is a program write signal, 18 is a second RAM, and 19 is a control circuit.
In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims

[Scope of utility model registration request]

A command reception circuit that inputs a command signal from the outside, outputs an interrupt signal, and outputs the command signal as multiple data signals in parallel; and inputs the multiple data signals output from the command reception circuit as parallel signals. A data bus that transmits the plural data signals as parallel signals and an interrupt signal output from the above command receiving circuit are input, and the plural data signals are input from the data bus, a hold signal is output, and a select signal is generated. A command decode circuit outputs an address count enable signal, inputs an interrupt signal output from the command receiver circuit, inputs a hold signal from the command decode circuit, and inputs and outputs multiple data signals from the data bus. a microprocessor that outputs a plurality of address signals as parallel signals; an address bus that inputs a plurality of address signals outputted from the microprocessor as parallel signals and transmits the plurality of address signals as parallel signals; An address counter that inputs the address count enable signal output from the command decode circuit, outputs multiple address signals as parallel signals to the address bus, and outputs a program write signal, and inputs the select signal output from the command decode circuit. ROM (Read Only Memory)
) and outputs an enable signal to RAM (Random
Access Memory) A select circuit that outputs an enable signal, and an R that inputs the ROM enable signal output from the select circuit, inputs a plurality of address signals from the address bus, and outputs a plurality of data signals to the data bus.
OM and the RAM enable signal output from the select circuit, input the program write signal output from the address counter, input multiple address signals from the address bus, and input multiple data signals to the data bus. A first RAM that has been output, a second RAM that inputs a plurality of address signals from the address bus and inputs a plurality of data signals to the data bus, and a second RAM that inputs a plurality of data signals from the data bus. Program control device with control circuit.