JPH0350255U - - Google Patents
Info
- Publication number
- JPH0350255U JPH0350255U JP10996189U JP10996189U JPH0350255U JP H0350255 U JPH0350255 U JP H0350255U JP 10996189 U JP10996189 U JP 10996189U JP 10996189 U JP10996189 U JP 10996189U JP H0350255 U JPH0350255 U JP H0350255U
- Authority
- JP
- Japan
- Prior art keywords
- signal
- memory
- signals
- memory control
- outputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 10
- 238000010586 diagram Methods 0.000 description 1
Description
第１図は本考案に係るメモリ制御装置の一実施
例を示す図、第２図は第１図装置の各部の信号の
タイムチヤートである。
１……メモリコントロール回路、２，３……遅
延素子、６，７，８……ライン、Ｍ１，Ｍ２，Ｍ
３……メモリ。
FIG. 1 is a diagram showing an embodiment of a memory control device according to the present invention, and FIG. 2 is a time chart of signals of various parts of the device shown in FIG. 1... Memory control circuit, 2, 3... Delay element, 6, 7, 8... Line, M1, M2, M
3...Memory.
Claims (1)
続されたｎ個のメモリと、 書込み／読み出し信号（以下単に、Ｗ／Ｒ信号
と記す）とセレクト信号をＴｄ・ｎ以上の周期で
出力する１個のメモリコントロール回路と（Ｔｄ
は前記各メモリの１アクセスにかかる時間）、 Ｗ／Ｒ信号とセレクト信号を受ける各メモリの
入力端子間を順に接続するとともに、一端がＷ／
Ｒ信号とセレクト信号を出力するメモリコントロ
ール回路の出力端子に接続されたラインと、 各メモリ間の前記ラインに挿入された遅延時間
Ｔｄの遅延素子と、 を備えたメモリ制御装置。[Scope of Utility Model Registration Claim] n memories each connected to a common address bus and a data bus, write/read signals (hereinafter simply referred to as W/R signals) and select signals of Td·n or more. One memory control circuit that outputs in cycles and (Td
is the time required for one access to each memory), the input terminals of each memory receiving the W/R signal and the select signal are connected in order, and one end is connected to the W/R signal.
A memory control device comprising: a line connected to an output terminal of a memory control circuit that outputs an R signal and a select signal; and a delay element having a delay time Td inserted in the line between each memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10996189U JPH0350255U (en) | 1989-09-20 | 1989-09-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10996189U JPH0350255U (en) | 1989-09-20 | 1989-09-20 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0350255U true JPH0350255U (en) | 1991-05-16 |
Family
ID=31658519
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10996189U Pending JPH0350255U (en) | 1989-09-20 | 1989-09-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0350255U (en) |
-
1989
- 1989-09-20 JP JP10996189U patent/JPH0350255U/ja active Pending
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