JPH0179164U - - Google Patents
Info
- Publication number
- JPH0179164U JPH0179164U JP1987174095U JP17409587U JPH0179164U JP H0179164 U JPH0179164 U JP H0179164U JP 1987174095 U JP1987174095 U JP 1987174095U JP 17409587 U JP17409587 U JP 17409587U JP H0179164 U JPH0179164 U JP H0179164U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- circuit
- signal
- built
- card
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000003213 activating effect Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 6
- 230000007334 memory performance Effects 0.000 description 1
Landscapes
- Credit Cards Or The Like (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図はこの考案の一実施例によるＩＣカード
のブロツク図、第２図はこの考案のＩＣカードが
接続されるシステム側の一部のブロツク図、第３
図はこの考案の他の実施例を示すブロツク図、第
４図は従来のＩＣカードのブロツク図、第５図は
従来のＩＣカードが接続されるシステムの一部ブ
ロツク図である。図において１はメモリー、２は
アドレス信号端子、３はデータ信号端子、４はメ
モリー制御信号端子、５はメモリーの諸性能を出
力する回路、６はメモリー性能出力制御信号端子
、７はデータバスである。なお、図中、同一符号
は同一又は相当部分を示す。
Figure 1 is a block diagram of an IC card according to an embodiment of this invention, Figure 2 is a block diagram of a part of the system to which the IC card of this invention is connected, and Figure 3 is a block diagram of a part of the system to which the IC card of this invention is connected.
FIG. 4 is a block diagram showing another embodiment of this invention, FIG. 4 is a block diagram of a conventional IC card, and FIG. 5 is a partial block diagram of a system to which the conventional IC card is connected. In the figure, 1 is a memory, 2 is an address signal terminal, 3 is a data signal terminal, 4 is a memory control signal terminal, 5 is a circuit that outputs various performances of the memory, 6 is a memory performance output control signal terminal, and 7 is a data bus. be. In addition, in the figures, the same reference numerals indicate the same or corresponding parts.
Claims (1)
内蔵するメモリーの諸性能（メモリー容量、アク
セスタイム等）をデータとしてメモリーと共有す
るデータバスに出力する回路を備えたことを特徴
とするＩＣカード。 (2) 上記回路を活性化させる信号は、内蔵する
メモリーを制御する諸信号とは別の信号を用いる
ことを特徴とする実用新案登録請求の範囲第１項
記載のＩＣカード。 (3) 上記回路を活性化させる信号として、通常
にメモリーを制御する信号レベルを越えたレベル
の信号を印加することによつて回路を活性化する
ことを特徴とする実用新案登録請求の範囲第１項
記載のＩＣカード。[Scope of claims for utility model registration] (1) In IC cards with built-in memory,
An IC card characterized by being equipped with a circuit that outputs various performances (memory capacity, access time, etc.) of built-in memory as data to a data bus shared with the memory. (2) The IC card according to claim 1, wherein the signal for activating the circuit is different from the signals controlling the built-in memory. (3) The scope of the utility model registration claim, which is characterized in that the circuit is activated by applying, as the signal for activating the circuit, a signal with a level exceeding the signal level that normally controls the memory. IC card described in Section 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987174095U JP2517540Y2 (en) | 1987-11-12 | 1987-11-12 | IC card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987174095U JP2517540Y2 (en) | 1987-11-12 | 1987-11-12 | IC card |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0179164U true JPH0179164U (en) | 1989-05-26 |
| JP2517540Y2 JP2517540Y2 (en) | 1996-11-20 |
Family
ID=31465970
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987174095U Expired - Lifetime JP2517540Y2 (en) | 1987-11-12 | 1987-11-12 | IC card |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2517540Y2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2011189730A (en) | 2010-02-22 | 2011-09-29 | Seiko Epson Corp | Memory device, board, liquid container, host device, and system |
| WO2011102440A1 (en) * | 2010-02-22 | 2011-08-25 | セイコーエプソン株式会社 | Storage device, substrate, liquid container and system |
-
1987
- 1987-11-12 JP JP1987174095U patent/JP2517540Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2517540Y2 (en) | 1996-11-20 |
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