JPH0270249U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 shows a memory control device according to an embodiment of the present invention, FIG. 2 shows a timing chart showing the operation of an embodiment of the invention, FIG. 3 shows a memory control device constructed using a conventional technique, and FIG. The figure is a timing chart showing the operation of the conventional technology. In FIG. 1, 1 is an address calculation circuit, 2 is a logical address register, 3 is an address state,
4 is a page register file, 5 is a physical page address register, 6 is a control data register, 7 is a decoder, 8 is a timing generation circuit, 9
10 is a selector control circuit, 11 is an expansion memory card, and 12 is a data bus. In addition, the same or equivalent parts in the figures are indicated by the same reference numerals.

Claims (1)

[Scope of utility model registration request] In a memory control device having an extended memory addressing function for a digital computer, an extended memory circuit, a circuit that identifies whether or not the extended memory circuit is connected and generates an identification signal, and a physical address generated using this identification signal. A memory control device comprising a selector that switches between an address from a circuit and an address from a logical address generation circuit.