JPS6335146U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a basic configuration diagram of an image memory access circuit according to the present invention, FIG. 2 is an embodiment of the image memory access circuit, FIG. 3 is an explanatory diagram showing the relationship between word address data and necessary data, and FIG. 4 is a timing chart when reading, FIG. 5 is an explanatory diagram showing the relationship between the input and output of the barrel shifter when reading, FIG. 6 is a timing chart when writing, and FIG. 7 is a diagram showing the relationship between the input and output of the barrel shifter when writing. Explanatory diagram, FIG. 8 is a timing chart when access is not made beyond the word area, FIG. 9 is an explanatory diagram showing the relationship between word address data and data accessed beyond the word address, and FIG. 10 is a conventional technique. FIG. 2 is an explanatory diagram showing memory access by. 1: Microprocessor, 2, 12-15: Image memory, 3: Address adder, 4: Memory select circuit, 5, 28, 29: Barrel shifter.

Claims (1)

[Claims for Utility Model Registration] In an image memory access circuit in which an image memory is accessed by a microprocessor across word boundaries of memory addresses, word data in the image memory is divided at arbitrary bit positions and read and written independently. and an address change circuit that switches the address from the microprocessor between the original address and an address adjacent thereto to access the image memory continuously in a time-division manner; An image memory access circuit further comprising a shifter that temporarily stores the word data to be input/output to the image memory and then replaces the word data using the divided bit positions as boundaries.