JPH0393948U - - Google Patents
Info
- Publication number
- JPH0393948U JPH0393948U JP195390U JP195390U JPH0393948U JP H0393948 U JPH0393948 U JP H0393948U JP 195390 U JP195390 U JP 195390U JP 195390 U JP195390 U JP 195390U JP H0393948 U JPH0393948 U JP H0393948U
- Authority
- JP
- Japan
- Prior art keywords
- pattern memory
- data
- bit
- multiplexer
- latch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
- 239000013256 coordination polymer Substances 0.000 description 1
Description
第１図は本考案に係るパターンメモリ書き込み
装置の一実施例を示す構成図、第２図はＣＰＵか
らパターンメモリにアクセスする際の従来の構成
図である。
１１……リードライト制御回路、１２……ラツ
チ、１３……マルチプレクサ、１４……マスクレ
ジスタ、１５……パターンメモリ、１６……ＣＰ
Ｕバス、１７，１８……バツフア。
FIG. 1 is a block diagram showing an embodiment of a pattern memory writing device according to the present invention, and FIG. 2 is a block diagram of a conventional structure when accessing a pattern memory from a CPU. 11... Read/write control circuit, 12... Latch, 13... Multiplexer, 14... Mask register, 15... Pattern memory, 16... CP
U bus, 17, 18...Batsuhua.
Claims (1)
アドレスの内容を読み出しそれを一時的に保存し
ておくためのラツチと、 ＣＰＵバスからのデータと前記ラツチの出力デ
ータを入力とし、外部データに基づきビツト単位
でいずれか一方の入力を選択して前記パターンメ
モリに送出するマルチプレクサと、 このマルチプレクサに与えるパターンメモリ書
換えビツト位置指定データを格納したマスクレジ
スタを具備し、パターンメモリの１データ書き込
みごとにビツト単位で書き込みが行えるようにし
たことを特徴とするパターンメモリ書き込み装置
。[Claim for Utility Model Registration] A pattern memory for storing data, a latch for reading and temporarily storing the contents of the address immediately before writing to the pattern memory, and data from the CPU bus. and a multiplexer that receives the output data of the latch as input, selects one of the inputs in bit units based on external data, and sends the selected input to the pattern memory, and a mask that stores pattern memory rewriting bit position designation data to be applied to the multiplexer. A pattern memory writing device characterized in that it is equipped with a register and is capable of writing bit by bit every time one data is written into a pattern memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP195390U JPH0393948U (en) | 1990-01-12 | 1990-01-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP195390U JPH0393948U (en) | 1990-01-12 | 1990-01-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0393948U true JPH0393948U (en) | 1991-09-25 |
Family
ID=31505839
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP195390U Pending JPH0393948U (en) | 1990-01-12 | 1990-01-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0393948U (en) |
-
1990
- 1990-01-12 JP JP195390U patent/JPH0393948U/ja active Pending
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