JPH0168525U - - Google Patents
Info
- Publication number
- JPH0168525U JPH0168525U JP1987163921U JP16392187U JPH0168525U JP H0168525 U JPH0168525 U JP H0168525U JP 1987163921 U JP1987163921 U JP 1987163921U JP 16392187 U JP16392187 U JP 16392187U JP H0168525 U JPH0168525 U JP H0168525U
- Authority
- JP
- Japan
- Prior art keywords
- memory card
- circuit unit
- card
- signal
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000007257 malfunction Effects 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
Landscapes
- Static Random-Access Memory (AREA)
Description
第１図はこの考案の一実施例によるメモリカー
ド書込み・読出し装置のブロツク図、第２図はメ
モリカード内のブロツク図、第３図はメモリカー
ド書込み・読出し装置の具体例を示すメモリカー
ドのアクセス回路図、第４図は従来のメモリカー
ド書込み・読出し装置のブロツク図である。
図中符号３はメモリカード、７はメモリカード
書込み・読出し装置、８は中央処理部、９はコネ
クタ、１０はカード検知回路部、１１はタイマ回
路部、１２はバツフア回路部、１３はバス、１４
はメモリカード誤動作防止回路である。なお、図
中同一符号は同一または相当部分を示す。
FIG. 1 is a block diagram of a memory card writing/reading device according to an embodiment of this invention, FIG. 2 is a block diagram of the inside of the memory card, and FIG. 3 is a memory card diagram showing a specific example of the memory card writing/reading device. Access Circuit Diagram FIG. 4 is a block diagram of a conventional memory card writing/reading device. In the figure, 3 is a memory card, 7 is a memory card writing/reading device, 8 is a central processing unit, 9 is a connector, 10 is a card detection circuit unit, 11 is a timer circuit unit, 12 is a buffer circuit unit, 13 is a bus, 14
is a memory card malfunction prevention circuit. Note that the same reference numerals in the figures indicate the same or corresponding parts.
Claims (1)
装着するメモリカード書込み・読出し装置におい
て、カードの装着あるいは取外しの状態を監視す
るカード検知回路部と前記カード検知回路部から
出力されたカードの装着あるいは取外しの信号を
入力し、装着時には遅延、取外し時には遅延せず
に該信号を出力する機能をもつタイマ回路部と前
記タイマ回路部より出力された信号により、中央
処理部とメモリカード間のバス信号の接続・非接
続を制御するバツフア回路部とを備えたことを特
徴とするメモリカードのアクセス回路。 A memory card writing/reading device for mounting a memory card equipped with a memory card detection terminal includes a card detection circuit unit that monitors the state of card mounting or removal, and a card detection circuit unit that monitors the card mounting or removal status outputted from the card detection circuit unit. A timer circuit unit has the function of inputting a signal and outputting the signal without delay when it is installed and without delay when it is removed, and the signal output from the timer circuit unit connects the bus signal between the central processing unit and the memory card. - A memory card access circuit characterized by comprising a buffer circuit section for controlling disconnection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987163921U JPH0168525U (en) | 1987-10-27 | 1987-10-27 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987163921U JPH0168525U (en) | 1987-10-27 | 1987-10-27 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0168525U true JPH0168525U (en) | 1989-05-02 |
Family
ID=31449081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987163921U Pending JPH0168525U (en) | 1987-10-27 | 1987-10-27 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0168525U (en) |
-
1987
- 1987-10-27 JP JP1987163921U patent/JPH0168525U/ja active Pending
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