JPS63147744U - - Google Patents
Info
- Publication number
- JPS63147744U JPS63147744U JP3807287U JP3807287U JPS63147744U JP S63147744 U JPS63147744 U JP S63147744U JP 3807287 U JP3807287 U JP 3807287U JP 3807287 U JP3807287 U JP 3807287U JP S63147744 U JPS63147744 U JP S63147744U
- Authority
- JP
- Japan
- Prior art keywords
- request signal
- write
- cpu
- storage device
- write request
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims 2
- 230000002265 prevention Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 5
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Description
第１図はこの考案に係る第１実施例の構成を示
すブロツク図、第２図は第２実施例の構成を示す
ブロツク図、第３図はタイマの構成を示すブロツ
ク図、第４図はタイマ関連の信号のタイムチヤー
トを示し、同図ａは第１実施例でのタイマ起動信
号のもの、同図ｂは第２実施例でのタイマ起動信
号のもの、同図ｃはタイマ信号のもの、第５図は
従来例の構成を示すブロツク図である。
符号説明、１：ＣＰＵ、２：メモリ、１０：ア
ドレスバス、１１：タイマ、１８：親制御装置、
２０：データバス。
FIG. 1 is a block diagram showing the configuration of the first embodiment of this invention, FIG. 2 is a block diagram showing the configuration of the second embodiment, FIG. 3 is a block diagram showing the configuration of the timer, and FIG. 4 is a block diagram showing the configuration of the second embodiment. The time charts of timer-related signals are shown in which a shows the timer start signal in the first embodiment, b shows the timer start signal in the second embodiment, and c shows the timer start signal in the second embodiment. , FIG. 5 is a block diagram showing the configuration of a conventional example. Description of symbols, 1: CPU, 2: Memory, 10: Address bus, 11: Timer, 18: Parent control device,
20: Data bus.
Claims (1)
要求信号端子と記憶装置側の書込み要求信号端子
との間に、所定条件によつてオンされ、あらかじ
め設定された時間の後にオフされるタイマーを設
けたことを特徴とする、記憶装置への書込み障害
防止回路。 (2) 実用新案登録請求の範囲第１項記載の方法
において、所定条件が、ＣＰＵからの書込み要求
信号有りであることを特徴とする、記憶装置への
書込み障害防止回路。 (3) 実用新案登録請求の範囲第１項記載の方法
において、所定条件が、ＣＰＵからの書込み要求
信号有りと別の外部からの割込み要求信号有りと
のＡＮＤ条件であることを特徴とする、記憶装置
への書込み障害防止回路。[Claims for Utility Model Registration] (1) Between the write request signal terminal on the CPU side of the microcomputer and the write request signal terminal on the storage device side, the signal is turned on under a predetermined condition and after a preset time has elapsed. A write failure prevention circuit for a storage device, characterized in that a timer that is turned off is provided. (2) A write failure prevention circuit for a storage device in the method according to claim 1, wherein the predetermined condition is the presence of a write request signal from a CPU. (3) The method described in claim 1 of the utility model registration claim, characterized in that the predetermined condition is an AND condition of the presence of a write request signal from the CPU and the presence of an interrupt request signal from another external source. Circuit for preventing write failures to storage devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3807287U JPS63147744U (en) | 1987-03-16 | 1987-03-16 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3807287U JPS63147744U (en) | 1987-03-16 | 1987-03-16 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63147744U true JPS63147744U (en) | 1988-09-29 |
Family
ID=30849975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3807287U Pending JPS63147744U (en) | 1987-03-16 | 1987-03-16 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63147744U (en) |
-
1987
- 1987-03-16 JP JP3807287U patent/JPS63147744U/ja active Pending
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