JPH01151338U - - Google Patents

Description

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of this invention, FIG. 2 is a diagram showing connections of a data bus terminal device of one embodiment, and FIG. 3 is a block diagram of a conventional data bus terminal device. , FIG. 4 is a diagram showing the connection of a conventional data bus terminal device. In the figure, 1 is a data bus line, 2 is an address bus line, 3 is a bus control device, 4 is a data bus terminal device, 5 is an external device, 6 is an interface circuit, 7 is a data memory, 8 is a receiving circuit, 9
10 is a transmission circuit, 10 is a command register, 11 is an address register, 12 is a comparator, 13 is a control circuit, 14 is a constant, 15 is a judgment circuit, 16 is an address setting permission signal line, and 17 is an address setting completion signal line. . Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Scope of utility model registration request] In a data bus terminal device of a data bus system in which a bus control device and a plurality of data bus terminal devices are connected via a bus line, a register that holds terminal address data sent from the bus control device and a terminal address are set. It has an address setting permission signal line that indicates which data bus terminal device should be used, and an address setting completion signal line that becomes significant when the terminal address is set. A data bus terminal device characterized in that address setting completion signal lines and address setting permission signal lines of all data bus terminal devices are connected in cascade in a tangential manner to an address setting permission signal line of the data bus terminal device.