JPS60112856U - information processing equipment - Google Patents
information processing equipmentInfo
- Publication number
- JPS60112856U JPS60112856U JP15483083U JP15483083U JPS60112856U JP S60112856 U JPS60112856 U JP S60112856U JP 15483083 U JP15483083 U JP 15483083U JP 15483083 U JP15483083 U JP 15483083U JP S60112856 U JPS60112856 U JP S60112856U
- Authority
- JP
- Japan
- Prior art keywords
- processing unit
- address
- signal
- output
- central processing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のマルチ・タスク機能を有する情報処理装
置の一例の要部のブロック図、第２図は本考案の一実施
例のブロック図、第３図は従来及゛゛び本考案の情報処
理装置を動作させるときの信号のタイミング図である。
１・・・・・・マイクロプロセッサ、２・・・・・・数
値演算フロセッサ、３・・・・・・アドレス・データ・
バス及ヒコントロール、４・・・・・・処理要求／処理
終了信号、５・・・・・・第１のアドレス／ステータス
信号、６・・・・・・インターラブド・フラグ監視回路
、７・・・・・・第２のアドレス／ステータス信号、３
・・・・・・判別回路、９・・・・・・条件成立信号、
１０・・・・・・論理積回路。Fig. 1 is a block diagram of the main parts of an example of a conventional information processing device having a multi-task function, Fig. 2 is a block diagram of an embodiment of the present invention, and Fig. 3 is a block diagram of information on the conventional information processing device and the present invention. FIG. 4 is a timing diagram of signals when operating the processing device. 1...Microprocessor, 2...Numerical processing processor, 3...Address/data/
bus control, 4... processing request/processing end signal, 5... first address/status signal, 6... interwoven flag monitoring circuit, 7. ...Second address/status signal, 3
...Discrimination circuit, 9...Condition fulfillment signal,
10...Logic product circuit.
Claims (2)
部に出力する機能と、相互処理装置と接続できる機能と
を有する中央処理装置と、該中央処理装置とアドレス・
データ・バス及びコントロールと処理要求／処理終了信
号とで接続される相互処理装置と、前記中央処理装置か
ら出力される第１のアドレス／ステータス信号を入力す
るインターラブド・フラグ監視回路と、前記中央処理装
置から出力される第２のアドレス／ステータス信号を入
力する判別回路と、前記インターラブド・フラグ監視回
路の出力と前記判別回路の出力との論理積をとり条件成
立信号を前記中央処理装置へ送信する論理積回路とを含
むことを特徴とする情報処理装置。(1) A central processing unit that has the function of outputting its own state and the state of the interlaced flag to the outside, and the function of being able to connect with mutual processing devices;
an interlaced flag monitoring circuit that receives a first address/status signal output from the central processing unit; a discriminating circuit that inputs a second address/status signal output from the processing device; ANDing the output of the interlaced flag monitoring circuit and the output of the discriminating circuit; and transmitting a condition fulfillment signal to the central processing unit; An information processing device comprising: an AND circuit that transmits data.
あるいは中央処理装置の内部のステータス時分割信号で
あり、第２のアドレス／ステータス信号がその出力時点
において中央処理装置あるいは相互処理装置のいずれが
動いているかを示す信号である実用新案登録請求の範囲
第（１）項記載の情報処理装置。(2) The first address/status signal is an address signal or an internal status time-sharing signal of the central processing unit, and the second address/status signal indicates whether the central processing unit or the mutual processing unit is operating at the time of output. The information processing device according to claim (1), which is a signal indicating whether the information processing device is registered as a utility model.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15483083U JPS60112856U (en) | 1983-10-05 | 1983-10-05 | information processing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15483083U JPS60112856U (en) | 1983-10-05 | 1983-10-05 | information processing equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60112856U true JPS60112856U (en) | 1985-07-31 |
Family
ID=30712827
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15483083U Pending JPS60112856U (en) | 1983-10-05 | 1983-10-05 | information processing equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60112856U (en) |
-
1983
- 1983-10-05 JP JP15483083U patent/JPS60112856U/en active Pending
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