JPS6082800U - Refresh device - Google Patents
Refresh deviceInfo
- Publication number
- JPS6082800U JPS6082800U JP17465883U JP17465883U JPS6082800U JP S6082800 U JPS6082800 U JP S6082800U JP 17465883 U JP17465883 U JP 17465883U JP 17465883 U JP17465883 U JP 17465883U JP S6082800 U JPS6082800 U JP S6082800U
- Authority
- JP
- Japan
- Prior art keywords
- refresh
- circuit
- signal
- state
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例のリフレッシュ装置のブロック図。第２
図は従来例のリフレッシュ装置の信号のタイムチャート
。第３図は本考案−実施例リフレッシュ装置のブロック
図。第４図は本考案による擬似リフレッシュ信号発生回
路図の詳細な回路図。第５図はその信号のタイムチャー
ト。
１・・・・・・フェッチ状態検出回路、２・・・・・・
リフレッシュ回路、３・・・・・・ドラム、４・・・・
・・ホールト状態検出部、５・・・・・・論理和回路、
６・・・・・・擬似ＩＪフレッシュ信号発生回路、７・
・・・・・擬似ホールト状態検出回路、８・・・・・・
論理回路、Ｓｏ、Ｓｌ・・・・・・ステータス信号、Ａ
ＬＥ・・・・・・上位アドレスラッチ信号。FIG. 1 is a block diagram of a conventional refresh device. Second
The figure is a time chart of signals of a conventional refresh device. FIG. 3 is a block diagram of a refresh device according to an embodiment of the present invention. FIG. 4 is a detailed circuit diagram of a pseudo refresh signal generation circuit according to the present invention. Figure 5 is a time chart of the signal. 1... Fetch state detection circuit, 2...
Refresh circuit, 3...Drum, 4...
... Halt state detection section, 5 ... OR circuit,
6...Pseudo IJ fresh signal generation circuit, 7.
...Pseudo-halt state detection circuit, 8...
Logic circuit, So, Sl...Status signal, A
LE... Upper address latch signal.
Claims (1)
力としてこのステータス信号の論理にしたがってフェッ
チ状態を検出するフェッチ状態検出回路と、 このフェッチ状態検出回路の出力にしたがって記憶装置
にリフレッシュ信号を送出するリフレッシュ回路と を備えたリフレッシュ装置において、 上記ステータス信号がホールト状態で上位アドレスラッ
チ信号が送出されている状態を検出する擬似リフレッシ
ュ信号発生回路と、 この擬似リフレッシュ信号発生回路の出力と上記フェッ
チ状態検出回路の出力との論理積を上記リフレッシュ回
路に入力する回路と を備えたことを特徴とするリフレッシュ装置。[Claims for Utility Model Registration] A fetch state detection circuit that receives a status signal sent from a microprocessor and detects a fetch state according to the logic of this status signal; and a refresh state in a storage device according to the output of this fetch state detection circuit. A refresh device that includes a refresh circuit that sends out a signal, a pseudo refresh signal generation circuit that detects a state in which the status signal is in a halt state and an upper address latch signal is sent out, and an output of the pseudo refresh signal generation circuit. A refresh device comprising: a circuit for inputting a logical product with the output of the fetch state detection circuit to the refresh circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17465883U JPS6082800U (en) | 1983-11-11 | 1983-11-11 | Refresh device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17465883U JPS6082800U (en) | 1983-11-11 | 1983-11-11 | Refresh device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6082800U true JPS6082800U (en) | 1985-06-07 |
Family
ID=30380181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17465883U Pending JPS6082800U (en) | 1983-11-11 | 1983-11-11 | Refresh device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6082800U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49122231A (en) * | 1973-03-22 | 1974-11-22 |
-
1983
- 1983-11-11 JP JP17465883U patent/JPS6082800U/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS49122231A (en) * | 1973-03-22 | 1974-11-22 |
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