JPS61168445U

JPS61168445U -

Info

Publication number: JPS61168445U
Application number: JP4942385U
Authority: JP
Priority date: 1985-04-03
Filing date: 1985-04-03
Publication date: 1986-10-18

Description

[Brief explanation of the drawing]

第１図はこの考案の一実施例を示すブロツク図
、第２図はこの考案の他の実施例を示すブロツク
図、第３図は従来のプロセツサの入出力バスを示
す、ブロツク図である。図において、１〜４は第１〜第４のレシーバ・
トランスミツタ、５はレシーバ、６，７は第１及
び第２のトランスミツタ、８はバス分配制御回郎
、ａはプロセツサのコマンド・アドレスバス、ｂ
は双方向性データバス、ｃは分配された第１のコ
マンド・アドレスバス、ｄは分配された第１の双
方向性データ・バス、ｅは分配された第２のコマ
ンド・アドレスバス、ｆは分配された第２の双方
向性データバスである。なお、各図中同一符号は
、同一または相当部分を示す。 FIG. 1 is a block diagram showing one embodiment of this invention, FIG. 2 is a block diagram showing another embodiment of this invention, and FIG. 3 is a block diagram showing an input/output bus of a conventional processor. In the figure, 1 to 4 are the first to fourth receivers.
5 is a receiver, 6 and 7 are first and second transmitters, 8 is a bus distribution control circuit, a is a processor command/address bus, b
is the bidirectional data bus, c is the first distributed command and address bus, d is the first distributed bidirectional data bus, e is the second distributed command and address bus, and f is the first distributed command and address bus. A distributed second bidirectional data bus. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims

[Scope of utility model registration request]

a first receiver-transmitter that inputs and outputs data from a bidirectional data bus of the processor and separates it into an input bus and an output bus; a second receiver-transmitter connected to the same data bus and having similar functions; a receiver for receiving commands and address data from the command and address bus of the processor;
a fourth receiver/transmitter, first and second transmitters for outputting commands and address data received by the receiver in two directions; data connected to the output bus of the first receiver/transmitter; It has a bus distribution control circuit that controls the direction of data passing through the first to fourth receivers/transmitters and controls the first and second transmitters by taking commands and addresses from the receiver. A bus distribution circuit characterized by: