JPS63126926U - - Google Patents

Info

Publication number
JPS63126926U
JPS63126926U JP1827787U JP1827787U JPS63126926U JP S63126926 U JPS63126926 U JP S63126926U JP 1827787 U JP1827787 U JP 1827787U JP 1827787 U JP1827787 U JP 1827787U JP S63126926 U JPS63126926 U JP S63126926U
Authority
JP
Japan
Prior art keywords
reset
input
output device
signal
flag
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1827787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1827787U priority Critical patent/JPS63126926U/ja
Publication of JPS63126926U publication Critical patent/JPS63126926U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案を実施した入出力装置の構成を
表わす図、第2図は本考案の入出力装置の動作を
表わすフローチヤートである。 1…ホスト計算機、2…入出力装置、3…コン
トローラ部、4…オンライン・ハード・リセツト
装置、5…信号検出回路、6…リセツト回路。
FIG. 1 is a diagram showing the configuration of an input/output device embodying the present invention, and FIG. 2 is a flowchart showing the operation of the input/output device of the present invention. DESCRIPTION OF SYMBOLS 1...Host computer, 2...I/O device, 3...Controller section, 4...Online hard reset device, 5...Signal detection circuit, 6...Reset circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] ホスト計算機に接続されて特有のコマンドを送
受信して動作する入出力装置において、通常の通
信では現われない特定の信号を解釈する信号検出
回路及びこの信号検出回路の信号によつてリセツ
ト・フラグを設定してこの入出力装置に対して一
定時間リセツト信号を発しその後前記フラグを解
除するリセツト回路からなるオンライン・ハード
・リセツト装置を有することを特徴とする入出力
装置。
In an input/output device that is connected to a host computer and operates by sending and receiving specific commands, a signal detection circuit interprets specific signals that do not appear in normal communication, and a reset flag is set by the signal of this signal detection circuit. 1. An input/output device comprising an online hard reset device comprising a reset circuit that issues a reset signal to the input/output device for a certain period of time and then releases the flag.
JP1827787U 1987-02-10 1987-02-10 Pending JPS63126926U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1827787U JPS63126926U (en) 1987-02-10 1987-02-10

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1827787U JPS63126926U (en) 1987-02-10 1987-02-10

Publications (1)

Publication Number Publication Date
JPS63126926U true JPS63126926U (en) 1988-08-19

Family

ID=30811806

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1827787U Pending JPS63126926U (en) 1987-02-10 1987-02-10

Country Status (1)

Country Link
JP (1) JPS63126926U (en)

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