JPH02108127U - - Google Patents
Info
- Publication number
- JPH02108127U JPH02108127U JP1623989U JP1623989U JPH02108127U JP H02108127 U JPH02108127 U JP H02108127U JP 1623989 U JP1623989 U JP 1623989U JP 1623989 U JP1623989 U JP 1623989U JP H02108127 U JPH02108127 U JP H02108127U
- Authority
- JP
- Japan
- Prior art keywords
- input
- pull
- resistor
- output
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 3
Landscapes
- Power Sources (AREA)
Description
第１図はこの考案の一実施例による信号１回路
の回路図、第２図は第１図に示した回路に於てデ
バイスの電源がＯＦＦの場合の等価回路、第３図
はセントロインタフエスの信号を説明するブロツ
ク図、第４図は従来の実施例における信号１回路
の回路図、第５図は第４図に示した回路に於て、
デバイスの電源がＯＦＦである場合の等価回路で
ある。
図に於て、１はコンピユータ、２はデバイス、
３はデータ信号、４はＳＴＲＯＢ信号、５はＡＣ
Ｋ信号、６はＢＵＳＹ信号、７はＳＬＣＴ信号、
８はＥＲＲＯＲ信号、９はＰＥ信号、１０はレシ
ーバ、１１，１３はプルアツプ抵抗、１２はドラ
イバー、１４はダイオードである。なお、図中同
一符号は同一、又は相当部分を示す。
Figure 1 is a circuit diagram of a signal 1 circuit according to an embodiment of this invention, Figure 2 is an equivalent circuit of the circuit shown in Figure 1 when the power of the device is OFF, and Figure 3 is a Centro interface circuit. 4 is a circuit diagram of the signal 1 circuit in the conventional embodiment, and FIG. 5 is a block diagram explaining the signals in the circuit shown in FIG. 4.
This is an equivalent circuit when the power of the device is OFF. In the figure, 1 is a computer, 2 is a device,
3 is data signal, 4 is STROB signal, 5 is AC
K signal, 6 is BUSY signal, 7 is SLCT signal,
8 is an ERROR signal, 9 is a PE signal, 10 is a receiver, 11 and 13 are pull-up resistors, 12 is a driver, and 14 is a diode. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
バイス間でデータ転送を行う装置において、入出
力インタフエスのレシーバ入力にプルアツプ抵抗
を有し、入出力デバイスのドライバ出力にプルア
ツプ抵抗を有し、さらに後者のプルアツプ抵抗と
直列にダイオードを有することを特徴とするデー
タ転送装置。 A device that transfers data between a computer's input/output interface and an input/output device has a pull-up resistor at the receiver input of the input/output interface, a pull-up resistor at the driver output of the input/output device, and a pull-up resistor for the latter. A data transfer device characterized by having a diode in series.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1623989U JPH02108127U (en) | 1989-02-14 | 1989-02-14 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1623989U JPH02108127U (en) | 1989-02-14 | 1989-02-14 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02108127U true JPH02108127U (en) | 1990-08-28 |
Family
ID=31228994
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1623989U Pending JPH02108127U (en) | 1989-02-14 | 1989-02-14 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02108127U (en) |
-
1989
- 1989-02-14 JP JP1623989U patent/JPH02108127U/ja active Pending
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