JPH0316619U - - Google Patents

Info

Publication number
JPH0316619U
JPH0316619U JP7726589U JP7726589U JPH0316619U JP H0316619 U JPH0316619 U JP H0316619U JP 7726589 U JP7726589 U JP 7726589U JP 7726589 U JP7726589 U JP 7726589U JP H0316619 U JPH0316619 U JP H0316619U
Authority
JP
Japan
Prior art keywords
processor
level
signal
level signal
set switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7726589U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP7726589U priority Critical patent/JPH0316619U/ja
Publication of JPH0316619U publication Critical patent/JPH0316619U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案の実施例に係る電子回路内蔵ス
イツチの構成を示す図である。 1…セツトスイツチ、2…プロセツサデータバ
ス、3…送信機、4…出力制御用電子回路部。
FIG. 1 is a diagram showing the configuration of a switch with a built-in electronic circuit according to an embodiment of the present invention. 1...Set switch, 2...Processor data bus, 3...Transmitter, 4...Output control electronic circuit section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 人為的作動によりオン・オフされるセツトスイ
ツチと、プロセツサに接続されるプロセツサデー
タバスと、プロセツサからのLレベル信号及びH
レベル信号のいずれか一方の信号指示に基づいて
セツトスイツチのオン・オフ状態を論理レベルに
変換して上記プロセツサデータバスに出力すると
ともに、プロセツサからのLレベル信号及びHレ
ベル信号のいずれか他方の信号指示に基づいてセ
ツトスイツチのオン・オフ状態の上記出力を無効
にする出力制御用電子回路部とを備えたことを特
徴とする電子回路内蔵スイツチ。
A set switch that is turned on and off by human operation, a processor data bus connected to the processor, and an L level signal and an H level signal from the processor.
The on/off state of the set switch is converted to a logic level based on the signal instruction of one of the level signals and outputted to the processor data bus, and the other of the L level signal and H level signal from the processor is converted to a logic level. 1. A switch with a built-in electronic circuit, comprising: an output control electronic circuit section that disables the above-mentioned output of the on/off state of the set switch based on a signal instruction.
JP7726589U 1989-06-30 1989-06-30 Pending JPH0316619U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7726589U JPH0316619U (en) 1989-06-30 1989-06-30

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7726589U JPH0316619U (en) 1989-06-30 1989-06-30

Publications (1)

Publication Number Publication Date
JPH0316619U true JPH0316619U (en) 1991-02-19

Family

ID=31619492

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7726589U Pending JPH0316619U (en) 1989-06-30 1989-06-30

Country Status (1)

Country Link
JP (1) JPH0316619U (en)

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