JPS62151250U - - Google Patents

Info

Publication number
JPS62151250U
JPS62151250U JP3917386U JP3917386U JPS62151250U JP S62151250 U JPS62151250 U JP S62151250U JP 3917386 U JP3917386 U JP 3917386U JP 3917386 U JP3917386 U JP 3917386U JP S62151250 U JPS62151250 U JP S62151250U
Authority
JP
Japan
Prior art keywords
circuit
station
outputs
signal
transmitting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3917386U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP3917386U priority Critical patent/JPS62151250U/ja
Publication of JPS62151250U publication Critical patent/JPS62151250U/ja
Pending legal-status Critical Current

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  • Selective Calling Equipment (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Description

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本考案の一実施例を示す回路図である
。第２図は第１図における回路中の各点における
信号波形図である。 ７……論理排他的オア回路、９……重畳回路、
１９……ケーブル、２０……ケーブル、２５……
第１の比較回路、２６……第２の比較回路、３０
……論理排他的オア回路、３３……フリツプフロ
ツプ回路。 FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a signal waveform diagram at each point in the circuit in FIG. 1. 7...Logic exclusive OR circuit, 9...Superimposition circuit,
19...cable, 20...cable, 25...
First comparison circuit, 26...Second comparison circuit, 30
...Logic exclusive OR circuit, 33...Flip-flop circuit.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 送信局と受信局とを二芯ケーブルで接続したも
のにおいて、送信局にはデータ信号とクロツク信
号とを入力した論理排他的オア回路と、該回路の
出力信号と上記データ信号とから３値信号を出力
する重畳回路を設け、受信局には高低異なる基準
値に設定した第１、第２の比較回路と、両比較回
路の出力を入力する論理排他的オア回路と両比較
回路の出力をセツトリセツト信号として入力する
フリツプフロツプ回路を設けたことを特徴とする
二芯式送受信装置。 In a device in which a transmitting station and a receiving station are connected by a two-core cable, the transmitting station has a logical exclusive OR circuit that inputs a data signal and a clock signal, and generates a ternary signal from the output signal of the circuit and the above data signal. The receiver station is equipped with a superimposition circuit that outputs , and the receiving station has first and second comparator circuits set to different high and low reference values, a logical exclusive OR circuit that inputs the outputs of both comparators, and a reset circuit that resets the outputs of both comparators. A two-core transmitting/receiving device characterized by being provided with a flip-flop circuit for inputting signals.
JP3917386U 1986-03-17 1986-03-17 Pending JPS62151250U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3917386U JPS62151250U (en) 1986-03-17 1986-03-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3917386U JPS62151250U (en) 1986-03-17 1986-03-17

Publications (1)

Publication Number Publication Date
JPS62151250U true JPS62151250U (en) 1987-09-25

Family

ID=30852101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3917386U Pending JPS62151250U (en) 1986-03-17 1986-03-17

Country Status (1)

Country Link
JP (1) JPS62151250U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306730A (en) * 2007-06-08 2008-12-18 Advantest Corp Transmission system, transmitter, receiver, and transmission method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008306730A (en) * 2007-06-08 2008-12-18 Advantest Corp Transmission system, transmitter, receiver, and transmission method

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