JPS62151250U - - Google Patents
Info
- Publication number
- JPS62151250U JPS62151250U JP3917386U JP3917386U JPS62151250U JP S62151250 U JPS62151250 U JP S62151250U JP 3917386 U JP3917386 U JP 3917386U JP 3917386 U JP3917386 U JP 3917386U JP S62151250 U JPS62151250 U JP S62151250U
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- station
- outputs
- signal
- transmitting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Selective Calling Equipment (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第1図は本考案の一実施例を示す回路図である
。第2図は第1図における回路中の各点における
信号波形図である。
7……論理排他的オア回路、9……重畳回路、
19……ケーブル、20……ケーブル、25……
第1の比較回路、26……第2の比較回路、30
……論理排他的オア回路、33……フリツプフロ
ツプ回路。
FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a signal waveform diagram at each point in the circuit in FIG. 1. 7...Logic exclusive OR circuit, 9...Superimposition circuit,
19...cable, 20...cable, 25...
First comparison circuit, 26...Second comparison circuit, 30
...Logic exclusive OR circuit, 33...Flip-flop circuit.
Claims (1)
のにおいて、送信局にはデータ信号とクロツク信
号とを入力した論理排他的オア回路と、該回路の
出力信号と上記データ信号とから3値信号を出力
する重畳回路を設け、受信局には高低異なる基準
値に設定した第1、第2の比較回路と、両比較回
路の出力を入力する論理排他的オア回路と両比較
回路の出力をセツトリセツト信号として入力する
フリツプフロツプ回路を設けたことを特徴とする
二芯式送受信装置。 In a device in which a transmitting station and a receiving station are connected by a two-core cable, the transmitting station has a logical exclusive OR circuit that inputs a data signal and a clock signal, and generates a ternary signal from the output signal of the circuit and the above data signal. The receiver station is equipped with a superimposition circuit that outputs , and the receiving station has first and second comparator circuits set to different high and low reference values, a logical exclusive OR circuit that inputs the outputs of both comparators, and a reset circuit that resets the outputs of both comparators. A two-core transmitting/receiving device characterized by being provided with a flip-flop circuit for inputting signals.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3917386U JPS62151250U (en) | 1986-03-17 | 1986-03-17 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3917386U JPS62151250U (en) | 1986-03-17 | 1986-03-17 |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62151250U true JPS62151250U (en) | 1987-09-25 |
Family
ID=30852101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3917386U Pending JPS62151250U (en) | 1986-03-17 | 1986-03-17 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62151250U (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008306730A (en) * | 2007-06-08 | 2008-12-18 | Advantest Corp | Transmission system, transmitter, receiver, and transmission method |
-
1986
- 1986-03-17 JP JP3917386U patent/JPS62151250U/ja active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2008306730A (en) * | 2007-06-08 | 2008-12-18 | Advantest Corp | Transmission system, transmitter, receiver, and transmission method |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS62151250U (en) | ||
JPS62151249U (en) | ||
JPH02133704U (en) | ||
JPS5914449U (en) | Synchronous signal input circuit | |
JPS6293829U (en) | ||
JPH0322966U (en) | ||
JPS6356826U (en) | ||
JPS6157785U (en) | ||
JPS59189798U (en) | Digital data memory write circuit | |
JPH0365327U (en) | ||
JPH01178638U (en) | ||
JPS5972558U (en) | Abnormality detection device for speed detection circuit of rotating body | |
JPS6237466U (en) | ||
JPS60177524U (en) | Optical communication receiver | |
JPS6438853U (en) | ||
JPH0170960U (en) | ||
JPS6124860U (en) | MFM signal demodulator | |
JPS61134182U (en) | ||
JPS59126335U (en) | Transmission/reception method | |
JPS594006U (en) | Duplex pulse output processing device | |
JPS6397938U (en) | ||
JPH01142031U (en) | ||
JPS5893046U (en) | semiconductor logic circuit | |
JPS59161732U (en) | latch circuit | |
JPS63185322U (en) |