JPS6397938U - - Google Patents

Info

Publication number
JPS6397938U
JPS6397938U JP1986191418U JP19141886U JPS6397938U JP S6397938 U JPS6397938 U JP S6397938U JP 1986191418 U JP1986191418 U JP 1986191418U JP 19141886 U JP19141886 U JP 19141886U JP S6397938 U JPS6397938 U JP S6397938U
Authority
JP
Japan
Prior art keywords
transmission circuit
encoder
data
logically
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1986191418U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1986191418U priority Critical patent/JPS6397938U/ja
Publication of JPS6397938U publication Critical patent/JPS6397938U/ja
Pending legal-status Critical Current

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  • Communication Control (AREA)
  • Maintenance And Management Of Digital Transmission (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Dc Digital Transmission (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の一実施例を示す回路図、第2
図は第1図におけるデータ処理装置のチエツク処
理フローチヤート、第3図は本考案の他の実施例
を示す回路図である。 1……エンコーダ、2,2A……ラインドライ
バ回路、3,3A……信号ケーブル、4,4A…
…データ処理装置、DR……ラインドライバ、
REC……ラインレシーバ。
Figure 1 is a circuit diagram showing one embodiment of the present invention;
This figure is a check processing flowchart of the data processing apparatus in FIG. 1, and FIG. 3 is a circuit diagram showing another embodiment of the present invention. 1... Encoder, 2, 2A... Line driver circuit, 3, 3A... Signal cable, 4, 4A...
...Data processing device, DR 1 ...Line driver,
REC 1 ...Line receiver.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] エンコーダのデイジタル出力を並列データ伝送
回路を通してデータ処理装置に収集するデータ収
集装置において、前記エンコーダの出力データに
代えて伝送回路の全ビツト入力を論理“1”又は
論理“0”との切換えを前記データ処理装置が指
令し、この指令に対する前記伝送回路の全ビツト
出力の論理“1”又は論理“0”の判定から該伝
送回路の正常、異常を判定する構成を特徴とする
エンコーダによるデータ収集装置。
In a data acquisition device that collects the digital output of an encoder to a data processing device through a parallel data transmission circuit, all bit inputs of the transmission circuit are switched to logic “1” or logic “0” instead of the output data of the encoder. A data acquisition device using an encoder, characterized in that a data processing device issues a command and determines whether the transmission circuit is normal or abnormal based on whether all bit outputs of the transmission circuit are logically “1” or logically “0” in response to the command. .
JP1986191418U 1986-12-12 1986-12-12 Pending JPS6397938U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1986191418U JPS6397938U (en) 1986-12-12 1986-12-12

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1986191418U JPS6397938U (en) 1986-12-12 1986-12-12

Publications (1)

Publication Number Publication Date
JPS6397938U true JPS6397938U (en) 1988-06-24

Family

ID=31145546

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1986191418U Pending JPS6397938U (en) 1986-12-12 1986-12-12

Country Status (1)

Country Link
JP (1) JPS6397938U (en)

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